Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5

Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5
by Admin on 06-11-2020 at 4:00 pm

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Register For This Web Seminar

Online – Jun 11, 2020
4:00 PM – 5:00 PM Europe/London

Online – Jun 11, 2020
4:00 PM – 5:00 PM US/Pacific

This is the fifth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above

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Questa Formal-Based Apps / Questa Formal Property Checking – What’s New in Functional Verification from Mentor: Session 4

Questa Formal-Based Apps / Questa Formal Property Checking – What’s New in Functional Verification from Mentor: Session 4
by Admin on 06-04-2020 at 4:00 pm

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Register For This Web Seminar

Online – Jun 4, 2020
4:00 PM – 5:00 PM Europe/London

Online – Jun 4, 2020
4:00 PM – 5:00 PM US/Pacific

This is the fourth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above

Read More

Protocol Verification with Questa VIP / Coverage Closure with Questa inFact

Protocol Verification with Questa VIP / Coverage Closure with Questa inFact
by Admin on 05-28-2020 at 4:00 pm

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Register For This Web Seminar

Online – May 28, 2020
4:00 PM – 5:00 PM Europe/London

Online – May 28, 2020
4:00 PM – 5:00 PM US/Pacific

This is the third of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above

Read More

Mentor at DVCON 2020!

Mentor at DVCON 2020!
by Daniel Nenni on 02-17-2020 at 6:00 am

DVCon 2020 SemiWiki

Are you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More


Mentor’s Questa verification tools now run on 64-bit ARM based servers

Mentor’s Questa verification tools now run on 64-bit ARM based servers
by Tom Simon on 10-10-2019 at 10:00 am

The server market has been undergoing changes in the last few years. The traditional go-to for server processors had been x86 based chips from Intel or AMD. However, if you go on Amazon AWS looking for EC2 instances, you will see the “A1” instance type, which is an ARM based instance. This is not what you might think at first. The A1 instance… Read More


Webinar: Visualizer and Optimizing Questa Performance

Webinar: Visualizer and Optimizing Questa Performance
by Daniel Payne on 09-25-2019 at 11:30 am

Mentor - A Siemens Business

Hosted by Oasis Sales and Trilogic, Inc.

Overview

Performance:  Every engineer wants more.  In this seminar we will look at using Questa vopt flow to gain raw simulator performance.  We will also look at how Questa Visualizer brings performance through debug efficiency. Finally we will see how working together, these tools can… Read More


MENTOR at DVCON 2019

MENTOR at DVCON 2019
by Daniel Nenni on 02-04-2019 at 7:00 am

The semiconductor conference season has started out strong and the premier verification gathering is coming up at the end of this month. SemiWiki bloggers, myself included, will be at the conference covering verification so you don’t have to. Verification is consuming more and more of the design cycle so I expect this event to … Read More


Mentor’s Symphony in Tune with AMS Designer Needs

Mentor’s Symphony in Tune with AMS Designer Needs
by Tom Simon on 11-14-2018 at 12:00 pm

Mixed signal simulation is a very hot topic these days. In modern designs, it is harder to draw a line between the analog and digital and work with them independently. Analog blocks are showing up everywhere. Even in what would have qualified as a digital design a few years ago, now designers need to look at things like PLLs, IOs and … Read More


Portable Stimulus enables new design and verification methodologies

Portable Stimulus enables new design and verification methodologies
by Jim Hogan on 10-19-2018 at 12:00 pm

My usual practice when investing is to look at startup companies and try to understand if the market they are looking to serve has a significant opportunity for a new and disruptive technology. This piece compiles the ideas that I used to form an investment thesis in Portable Stimulus. Once collected, I often share ideas to get feedback.… Read More