Ad hoc digital design verification approaches ran out of steam at least a decade ago when designs got intractably large to make it feasible to keep track of everything with pen and paper and excel. But analog design has remained largely ad hoc to this day. The designer runs spice, looks at the waveforms that come out and decide whether… Read More
Tag: questa
Coverage Driven Verification for Analog?
We know there is a big divide between analog and digital design methodologies, level of automation, validation and verification processes, yet they cannot stay without each other because any complete system on a chip (SoC) demands them to be together. And therefore, there are different methodologies on the floor to combine analog… Read More
Pizza con Questa
Last week I went to a lunch and learn at Mentor about their Questa formal product given by Kurt Takara. Like everyone else these days, Questa is packaged as a number of Apps for doing different tasks. Formal verification is different from other EDA tools in that different approaches can be used for different sub-tasks. There are three… Read More
Accelerating SoC Verification Through HLS
Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large SoCs with complex architectures and several constraints of area, performance,… Read More
Mentor’s New Enterprise Verification Platform
I spent the morning at Mentor where they announced their new enterprise verification platform. This was a general announcement but was attended by a lot of the international press who were over on a GlobalPress tour (the event that used to take up camp at Chaminade).
But first Wally Rhines spent 30 minutes giving a nice overview of… Read More