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Coverage Driven Analog Verification

Coverage Driven Analog Verification
by Paul McLellan on 11-25-2014 at 7:00 am

Ad hoc digital design verification approaches ran out of steam at least a decade ago when designs got intractably large to make it feasible to keep track of everything with pen and paper and excel. But analog design has remained largely ad hoc to this day. The designer runs spice, looks at the waveforms that come out and decide whether or not they are acceptable. But now even in analog design this sort of undisciplined approach is in turn starting to change away from the traditional methodology in the diagram below.

There are a number of reasons for this. One is that digital design (and the unit test approach to software development) has such clear advantages that it is silly for analog design not to piggyback on the experience. At the same time more and more analog, especially in the more advanced processes, is relatively simple analog design with very complex digital logic used to trim it, sometimes called digital controlled analog or DCA, meaning that the analog and the digital aspects of the design need to be verified together.

Digital design and analog designs are complementary in some ways. Digital is straightforward to design (at least from the RTL onwards we have a working methdology) but verification is very hard due to the impossibly large state space. Analog, on the other hand, is easy to specify but actually designing the blocks is extremely hard. As a result digital designers adopted coverage driven verification (CDV), based on assertions and property checking and verification planning to ensure that verification cycles are not wasted on things that have already been verified.

With the increased complexity of analog designs and IP due to the implementation of an increased number of features and functionalities as well as greater challenges due to the large variation of device characteristics in nanometer technologies, verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This work aims to extend common traits of CDV as used in digital verification to analog verification. This would bring standardization of the analog verification process.

A further driver is that standards for aerospace and automotive, such as ISO 26262, will no longer accept an ad hoc approach to requirements tracking. This too drives towards a much more formal approach:

  • specification of all requirements, whether analog or digital
  • a test plan and test cases to verify whether each requirement is met
  • metrics for measuring coverage of the tests in the test plan
  • a system for tracking requirements to ensure that they are all met and to reduce duplication of unnecessary tests

Mentor has a new white paper A Complete Analog Design Flow for Verification Planning and Requirement Tracking by Atul Pandey, Guido Clemens, Marius Sida. The whitepaper describes building a flow for CDV based on ICanalyst, Questa and ReqTracer.

You can download the whitepaper here.

More articles by Paul McLellan…

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