Accelerating Design and Manufacturing at the 25th Annual IEEE Electronic Design Process Symposium

Accelerating Design and Manufacturing at the 25th Annual IEEE Electronic Design Process Symposium
by Camille Kokozaki on 09-05-2018 at 12:00 pm

25th annual IEEE Electronic Design Process Symposium
Accelerating Design and Manufacturing
September 13 & 14, 2018, SEMI, 673 S. Milpitas Blvd, Milpitas, CA 95035

This year marks a milestone in EDPS’s history as it turns 25. The event will be held at SEMI’s new headquarter facility and will provide a forum for EDA, foundry … Read More


Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA

Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
by Herb Reiter on 04-14-2016 at 12:00 pm

Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More


IoT Workshop in Beautiful Monterey California!

IoT Workshop in Beautiful Monterey California!
by Daniel Nenni on 03-27-2016 at 8:00 pm

Image RemovedIt is that time of year again, the EDPS Workshop at the Tides Hotel in Monterey. This year will start out with a keynote on IoT from Serge Leef, VP of New Ventures and GM of the System-level Engineering Division at Mentor Graphics. Serge started his career at Intel followed by Microchip and Silicon Graphics. He has been… Read More


Speaking about the Internet of Trust on April 21

Speaking about the Internet of Trust on April 21
by Don Dingee on 03-14-2016 at 4:00 pm

Five minutes to ruin a reputation built over 20 years, as Warren Buffett put it, holds true in personal relationships. On the Internet of Things, reputations can disappear in five seconds. How do we move from merely intelligent Things to a level where devices have to be Trusted?… Read More


EDPS: Fins and FinFETs

EDPS: Fins and FinFETs
by Paul McLellan on 04-02-2015 at 7:00 am

Image RemovedLook at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic… Read More


FD-SOI Better Than FinFET?

FD-SOI Better Than FinFET?
by Paul McLellan on 04-27-2014 at 9:16 am

As I said earlier in the month, I was going to be talking about FD-SOI at the Electronic Design Process Symposium (EDPS) in Monterey. I am not especially an expert on FD-SOI but I know enough to be dangerous and given that we were already talking about FinFET and 3D/2.5D chips, it fitted in nicely.

The 10,000 foot view is that FD-SOI has… Read More


IP the eSilicon Way

IP the eSilicon Way
by Paul McLellan on 04-22-2014 at 9:51 pm

Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn’t know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.

At Electronic Design Process Symposium (EDPS) held last … Read More


EUV Slips a Year Per Year…Or More

EUV Slips a Year Per Year…Or More
by Paul McLellan on 04-19-2014 at 1:54 am

I was at EDPS in Monterey the last couple of days. It is one of the most interesting conferences to attend. Go next year since you already missed it this year. It is not big but the quality of the content is high. Historically the dinner in the middle is in the Monterey Yacht Club and there is a keynote speech. A few years ago it was me but this… Read More


FD-SOI, FinFET, 3D in Monterey

FD-SOI, FinFET, 3D in Monterey
by Paul McLellan on 04-09-2014 at 5:40 pm

Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles).… Read More


Handel Jones on FD-SOI vs FinFET

Handel Jones on FD-SOI vs FinFET
by Paul McLellan on 03-20-2014 at 1:27 am

Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More