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Handel Jones on FD-SOI vs FinFET

Handel Jones on FD-SOI vs FinFET
by Paul McLellan on 03-20-2014 at 1:27 am

Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis takes into account depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.

It turns out that at 28nm, FD-SOI is already marginally cheaper than bulk planar CMOS. It has a smaller number of masks and fewer processing steps. The difference is a bit bigger at 20nm. At 16nm the comparison with FinFET shows that FD-SOI is a lot cheaper. See the diagram above.

He then goes on to analyze die costs, taking into account gross die per wafer and yield. That results in the graph above. The money quote is that:At 14nm/16nm, the FD-SOI die cost for a 100mm[SUP]2[/SUP] die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

For the very highest performance SoCs, then FinFET is presumably worth the cost. But for anything not on the bleeding edge then FD-SOI might be a more cost-effective solution. FD-SOI, like FinFET, has much lower leakage than bulk, but FinFET can have issues with dynamic power due to the high gate capacitance.

STMicroelectronics has been the trailblazer for FD-SOI and has working products in 28nm. It is not a theoretical alternative to FinFET, it is real. The whole supply chain is starting to fall into place.

 At EDPS in Monterey on 17th/18th April I will be talking about FD-SOI in more depth. My working title is Praise FD-SOI, slag FinFETs but maybe I’ll find something a little more politically acceptable. There are also presentations that afternoon on FinFETs (praise FinFETs, slag FD-SOI perhaps) and on 3D-IC (praise TSVs, slag Moore’s Law completely). Come along and watch the wrestling match. Moore’s Law as we used to know it is over: 28nm won. It is not just cheaper than every process that came before it, it is cheaper than every process that is going to come after it. Details on EDPS are here.

The final conclusions of the white-paper:

  • at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
  • the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.

Handel’s white-paper is here.

More articles by Paul McLellan…

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