WP_Term Object
    [term_id] => 47
    [name] => Magillem
    [slug] => magillem
    [term_group] => 0
    [term_taxonomy_id] => 47
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 14
    [filter] => raw
    [cat_ID] => 47
    [category_count] => 14
    [category_description] => 
    [cat_name] => Magillem
    [category_nicename] => magillem
    [category_parent] => 157
    [is_post] => 1

TLM Modeling Environment Goes Commercial

TLM Modeling Environment Goes Commercial
by Daniel Payne on 03-20-2014 at 6:00 pm

The most successful EDA companies typically choose a domain where they have deep knowledge, then serve a few leading-edge customers that are willing to work with a start-up in exchange for early access to that new technology. The theory is that if you can satisfy the leading-edge customer then you can also satisfy the rest of the market segment. Magillemis one such EDA company that has worked closely with STMicroelectronics over the years on ESL tools that use IP-XACTand help manage complexity, interoperability and design re-use for SoC designers. This week Magillem announced something a little bit different, because they have signed an OEM agreement with STMicroelectronics to offer ST’s TLM (Transaction Level Modeling) modeling environment and methodology.

The EDA industry has provided tools to model at a variety of levels, and each for a different purpose:

  • Transistor-level, for SPICE circuit simulation and layout versus schematic checking
  • Gate-level, for functional simulation and fault modeling
  • Cell-level, for collections of transistors and gates
  • Register Transfer Level (RTL), a language based approach using VHDL, Verilog or SystemVerilog. RTL can be automatically synthesized into gate or cell levels.
  • Transaction Level Modeling (TLM), a higher-lever approach to modeling a digital system, where details of communication between modules are separated from the details of the implementation of functional units or of the communication architecture. (Source: Wikipedia)

Magillem already offered five tools for SoC design:

  • Magillem IP-XACT Packager
  • Magillem Platform Assembly
  • Magillem Register View
  • Magillem Generator Studio
  • Magillem Flow Control

This new TLM modeling fills a product gap for Magillem, and will allow SoC designers to build and analyze virtual platforms using SystemC, one of the faster growing segments in EDA today. SystemC is a set of C++ classes and macros which provide an event-driven simulation interface in C++ (Source: Wikipedia). SystemC is a standard defined by Accellera, and Magillem is a board member of Accellera.

Expect more product details and availability to be announced as we get closer to DAC in June. There is a press release at the Magillem site with quotes from Philippe Magarshack, Executive Vice-President and General Manager, Design Enablement and Services STMicroelectronics and Cyril Spasevski, Chair and CTO of Magillem. You can also visit with Magillem at CHIPEX in Tel Aviv, Israel at the end of April.

lang: en_US

0 Replies to “TLM Modeling Environment Goes Commercial”

You must register or log in to view/post comments.