EDPS: Fins and FinFETs

EDPS: Fins and FinFETs
by Paul McLellan on 04-02-2015 at 7:00 am

 Look at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic Design Process Symposium (EDPS) which is held as usual in the Monterey Beach Hotel. This year it is Thursday and Friday April 23rd and 24th.

Register here with Promo Code: SemiWiki-EDPS2015

I blogged earlier this weekabout the Linley Mobile Conference and the observant among you will notice that they overlap, the second day of Linley is the first day of EDPS.

Apurna Dey of Cadence is the general chair and opens the meeting on Thursday at (I’m guessing, the program doesn’t have any times at all yet) 9am.

The first session is chaired by Dan Nenni and is on FinFET vs FD-SOI. It kicks off with a keynote from Tom Dillinger of Oracle (think Sun) followed by a panel session with Tom, Kelvin Low of Samsung Foundry, Boris Murman of Stanford University, Marco Brambilla of Synapse Design, and Jamie Shaeffer of GlobalFoundries:

The emergence of multiple transistor technology options at today’s deep submicron process nodes introduces a variety of power, performance, and area tradeoffs. This session will start with an overview of the FinFET and Fully-Depleted Silicon-on-Insulator devices (FD-SOI, also known as Ultra-Thin Body SOI), in comparison to traditional bulk planar transistor technology. The session will then delve into a detailed discussion of the architectural and circuit implementation tradeoffs of these new offerings, to assist designers make the right choice for their target application.

That takes us up to lunch. After lunch it is Multi-Die Design Challenges and Applications, which I think is just a long title for 3DIC. The sessions are:

  • Herb himself on 3D-IC EcoSystem Today and What’s Next
  • Brandon Wang of Cadence on Versatile 3D-IC Design Environment
  • Dusan Petranovic of Mentor on Verification and Extraction of 3D Stack Components Interaction
  • Rich Rice of ASE on Multi-die Packaging—How Ready Are We?

Then a change of scenery with Hybrid Virtual Platforms moderated by Gary Smith (himself, as Regis McKenna’s business card used to say) and John Swan (now of Intel). Sessions are:

  • Vikramheet Singh of nVidia on Hybrid Pre-Silicon Platforms for Accelerated SW Development
  • Vinoo Srinivasan of Intel on Hybrid VP – Are they the highbred Virtual Platforms?
  • Frank Schirrmeister of Cadence on Stop Abstracting! Use the Real Design Earlier for Software Verification Using Hybrid Approaches
  • Russel Klein of Mentor on The Need For Speed

 After that it is off to dinner at the Monterey Yacht Club down on the old wharf. The dinner keynote is by Dileep Bhandarkar of Qualcomm titled The Yellow Brick Road of Semiconductor Technology. The talk will provide a historical perspective on how the computer industry has taken advantage of Moore’s Law and how we got to the era of multicore processors. The talk will also address some of the challenges facing the industry in the future.

And so to bed. Next morning we wak up to Low Power Day. The keynote is by Jim Kardach of FinSix on Low Power Design, Standards and Evolution.

Naresh Sehgal then chairs a session on Low Power Technologies and Ecosystems. Presentations are by:

  • Steve Carlson of Cadence on Low-power and Mixed Signal Solutions
  • Pat Sheridan of Synopsys on Power-aware Architecture Design for Multicore SoCs
  • Bernard Murphy of Atrenta on Low Power on the Bleeding Edge
  • Prasad Subramaniam of eSilicon on Low Power Design Methodologies

After lunch, Andrew Khang of UCSD gives a keynote on EDA/ESL Low Power Design Trends, ITRS/CAD and Tools. That wins the prize for getting the most acronyms into a title.


There is then a panel session with Brian Fuller of Cadence as the emcee. The subject is Can Power Go Any Lower or Have We Hit Almost Hit the Floor, Especially For IoT Devices?which wins this conference’s prize for getting the most words into a title (they could have got bonus points for spelling out IoT in full). The panel participants are Jim Kardach along with the presenters from the previous session.

Nahresh Sehgal and Apurna Dey close out and send us all back on our way up Highway 1.

Complete program info and a link for registration is here. Be sure and use promo code SemiWiki-EDPS2015 for a reduced rate.


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