Accelerating Design and Manufacturing at the 25th Annual IEEE Electronic Design Process Symposium

Accelerating Design and Manufacturing at the 25th Annual IEEE Electronic Design Process Symposium
by Camille Kokozaki on 09-05-2018 at 12:00 pm

25th annual IEEE Electronic Design Process Symposium
Accelerating Design and Manufacturing
September 13 & 14, 2018, SEMI, 673 S. Milpitas Blvd, Milpitas, CA 95035

This year marks a milestone in EDPS’s history as it turns 25. The event will be held at SEMI’s new headquarter facility and will provide a forum for EDA, foundry and design industries to address design and manufacturing issues. The Symposium will focus on acceleration methods for the design and manufacturing processes.

Key changes in designs and design methodologies continue to be an EDPS focus. Leading industry members will be sharing their challenges and solutions in this vibrant symposium. Real design in a real conversation setting will be discussed. EDPS 2018 sessions are based on the following themes:

  • Cyber Systems Design with emphasis on security
  • Innovative Designs and Design Techniques including Machine Learning in System Design and EDA
  • Smart Manufacturing – Increased cooperation between design & manufacturing (2.5/3D-IC Assembly and Test, Die-Pkg-Board CO-design flow, Flexible Hybrid Electronic)
  • System reliability with a special focus on ADAS, 5G, and Photonics.

The event will conclude with a panel discussion to analyze Blockchain’s role in EDA and Design. The Thursday evening banquet is co-located with the ESDA event “Building Start-Ups to Successful Exit” moderated by Jim Hogan.

Other Keynote Speakers include Chris Rowen, (CEO, BabbLabs) with an address entitled ‘Deep Learning Revolution – From Theory to Impact’. Andrew Kahng (Prof Computer Science & Engineering, UCSD) discussing ‘Evolutions of EDA, Manufacturing, and Design’. Simon Johnson (Sr Principal Engineer, Intel) will outline ‘Hardware-Based Security’.

Visit http://edpsieee.ieeesiliconvalley.org/ for additional details.

This event will offer time for Q&A after every presentation and plenty of networking time among ~ 100 attendees and speakers.

The event is sponsored by IEEE’s Council on Electronic Design Automation (CEDA) and Silicon Valley’s IEEE Computer Society and corporate Sponsors Ansys, Mentor Graphics, Intel with Semi as Associate Sponsor and IEEE’s Electronics Packaging Society as technical co-sponsor

In case you missed the early bird registration, EDPS is happy to offer a promo code “chipexpert-edps” that will provide $50 off the registration.You can register at edps2018.eventbrite.com and a complete schedule is available at ieee-edps.org and is attached here.

About EDPS:
The 2018 Electronic Design Process Symposium is the leading forum for advanced chip and systems development and CAD methodologies. As we approach the end of Moore’s law scaling, innovative packaging techniques are becoming increasingly important as package, board and other system components drive significant cost reduction. Innovative and smart manufacturing methodologies and flows are also becoming increasingly important. Since algorithmic development is changing rapidly, smart manufacturing enabling reduced NRE and faster time to market are critical.

Among other things, data center applications require heightened cybersecurity. 3DIC chip stacking of host processor and accelerator avoids exposing the bus between them to cyber-attacks. Implementation of machine and deep learning algorithms provide a higher level of defense against hacking. Cybersecurity is also very critical in system designs such as the ones found in automotive applications.

Reliability at the system level as well as at the package and chip level is impacted by ESD and thermal issues. Guaranteed performance needs to take aging and power into account. Newer interconnect, changing communication protocols and a wide range of operating conditions for systems require enhanced reliability for power and signal interconnects.

Heterogeneous integration of chips in high-performance processes and chips in mature process nodes allows higher performance and better yield optimization. More flexible system level partitioning will lead the way to new products’ development. Architectural modularity and IP re-use will enable higher performance at lower total system cost. New FPGA methodologies, especially embedded FPGA will see extensive use.

And last but not the least, machine learning is permeating all fields of system design and design tools.

A Trip Down Memory Lane:22282-daniel-nenni-edps.jpg

The picture is of SemiWiki founder Daniel Nenni at the 2015 EDPS in Monterey:

The first session was chaired by Daniel Nenni and is on FinFET vs FD-SOI. It kicked off with a keynote from Tom Dillinger of Oracle (think Sun) followed by a panel session with Tom, Kelvin Low of Samsung Foundry, Boris Murman of Stanford University, Marco Brambilla of Synapse Design, and Jamie Shaeffer of GlobalFoundries:

The emergence of multiple transistor technology options at today’s deep submicron process nodes introduces a variety of power, performance, and area tradeoffs. This session will start with an overview of the FinFET and Fully-Depleted Silicon-on-Insulator devices (FD-SOI, also known as Ultra-Thin-Body SOI), in comparison to traditional bulk planar transistor technology. The session will then delve into a detailed discussion of the architectural and circuit implementation tradeoffs of these new offerings, to assist designers to make the right choice for their target application.

Detailed 2018 Program Info: