PCIe Webinar Banner
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3970
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3970
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA

Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
by Herb Reiter on 04-14-2016 at 12:00 pm

Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.

– how can you serve applications that don’t require a billion units over their life time and can’t pay back a large NRE?
– how can your company continue to grow if it needs to invest such large sums and “bet the farm” on a single project?
– how can you pack logic, memory, analog, RF, MEMS,… and other functions economically into a 7 nm SoC?

The Electronic Design Process Symposium (EDPS) 2016 will address these and many other questions on Thursday afternoon, April 21.

EDA, IC design and IC packaging experts will present their capabilities in support of packing multiple dies into one IC package, suggest where and how to combine multiple dies in a 2.5 or 3D-IC, or consider wafer-level packing. Half of the 2-hour session is reserved for discussing the benefits as well as answering your questions during the panel discussion.

Herb Reiter, from eda 2 asic, will introduce the session’s subject, outline his new consulting role at the Electronic System Design Alliance (formerly known as EDAC), highlight why our industry needs to complement continued shrinking with multi-die IC technologies, suggest what the represented industry segments need to do to further grow market acceptance of these innovations, introduce the panelists and also moderate the discussion with the audience.

Riko Radojcic, well known for his role as 3D-IC evangelist at Qualcomm, will share his vast expertise in how to determine cost advantages and technical reasons for choosing a multi-die IC technology for a specific application.

Mentor Graphic’s Dusan Petranovic will present and discuss the importance of accurate modeling and thorough verification for cost-effective and reliable multi-die ICs.

For companies who do not have sufficient in-house resources to execute a multi-die IC design and/or want expert advice for engaging the right supply chain partners, plan to develop a multi-die IC design methodology, want assistance to ramp up volume production for such ICs or other reasons, Design Services companies are ready and eager to offer their expertise. Asim Salim will represent Open Silicon, outline the team’s expertise and their important role in the Multi-die IC EcoSystem. See below the EcoSystem’s key segments and their individual roles.

The next speaker, Ivor Barber, has many years of experience in advanced IC packaging and will present why Xilinx chose to pioneer multi-die IC technology several years ago already. He’ll outline technical and business reasons for the success of Xilinx’ “Stacked Silicon Interposer Technology” (SSIT).

Paul Silvestri from Amkor, a leading IP Packaging and Test corporation, will show Amkor’s portfolio of traditional and recently introduced advanced IC packaging technologies, which include a very cost-effective family of Fan-Out Wafer-level packages.

After these brief presentations our experts will be available for an additional hour to answer questions from the audience. Herb will moderate this panel discussion and make sure that every attendee can see that the EcoSystem in support of multi-die ICs has made significant progress in the last few years. Now many partners can offer you viable products and services for your first (or next) multi-die IC design. You also can integrate one of your proven SoCs — in die-form — together with other die-level IP, such as a memory cube, in a multi-die IC package and enjoy the performance, power, form-factor and system cost benefits versus individual, fully packaged ICs on a PC board.

Just in case that you are still hesitant to fit EDPS into your busy schedule, click on the pointers below. The first one leads you to a recent article that describes how NXP/Freescale use their RCP interposer technology for a 77GHz automotive radar application: http://www.systemplus.fr/wp-content/uploads/2016/03/NXP_MR2001_Freescale_Radar-Chipset_Flyer_SPC_v2.pdf

The second pointer directs you to last week’s Nvidia announcement of the Tesla P100 GPU and their DGX-1 GPU server, utilizing four memory cubes surrounding a GPU on an interposer: http://www.eetimes.com/document.asp?doc_id=1329368

For many more articles about concrete applications of multi-die ICs and a lot of other information about the Multi-die IC EcoSystem, please click on this pointer and download the 324 page Multi-die IC Design Guide from the Electronic System Design Alliance’s website: http://www.esd-alliance.org/industry/publications

More about EDPS and other valuable sessions at: http://edpsieee.ieeesiliconvalley.org/edps_program.php

SemiWiki-EDPS2016promo code for a $50 savings.

See you at EDPS in Monterey next week….Herb

Share this post via:


0 Replies to “Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA”

You must register or log in to view/post comments.