FD-SOI, FinFET, 3D in Monterey

FD-SOI, FinFET, 3D in Monterey
by Paul McLellan on 04-09-2014 at 5:40 pm

Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles).… Read More


Handel Jones on FD-SOI vs FinFET

Handel Jones on FD-SOI vs FinFET
by Paul McLellan on 03-20-2014 at 1:27 am

Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More


A bird told me the EDPS Monterey Conference was a great success

A bird told me the EDPS Monterey Conference was a great success
by Camille Kokozaki on 04-20-2013 at 8:10 pm

The 20th annual Electronic Design Process Symposium (EDPS) held April 18-19 at the Monterey Beach Hotel in Monterey California was an unqualified success. I know this because a bird (seagull?) sitting on the window sill of the conference room was so captivated by the fascinating insight provided by a number of luminaries that … Read More


Ivo Bolsens’ Keynote on the All-Programmable SoC

Ivo Bolsens’ Keynote on the All-Programmable SoC
by Paul McLellan on 04-13-2013 at 8:00 pm

Ivo Bolsens, the CTO of Xilinx, is giving the opening keynote at the Electronic Design Process Symposium (EDPS) in Monterey on Thursday and Friday this coming week. The title of his keynote is The All Programmable SoC – At the Heart of Next Generation Embedded Systems. He covers a lot of ground but the core of his presentation… Read More


3D IC: Are We There Yet?

3D IC: Are We There Yet?
by Paul McLellan on 04-13-2013 at 4:42 pm

For the last few years, thru silicon via (TSV) based ICs have been looming in the mist of the future. Just how far ahead are they? Xiliinx famously has a high-end gate-array in production on a 2.5D interposer, Micron has a memory cube, TSMC has done various things in 3D that it calls CoWoS (chip on wafer on substrate), Qualcomm have been… Read More


TSMC to Talk About 10nm at Symposium Next Week

TSMC to Talk About 10nm at Symposium Next Week
by Daniel Nenni on 04-02-2013 at 8:05 pm

Given the compressed time between 20nm and 16nm, twelve months versus the industry average twenty four months, it is time to start talking about 10nm, absolutely. Next Tuesday is the 19th annual TSMC Technology Symposium keynoted of course by the Chairman, Dr. Morris Chang.

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April 17-19: Overbooked!

April 17-19: Overbooked!
by Paul McLellan on 04-01-2013 at 4:23 pm

For three days in a couple of weeks time there is a crash of conferences, spread out all over the extended Bay Area.

Firstly, from 17-19th April at the Santa Clara Hyatt is the Linley Mobile Conference. This covers all things microprocessor in the mobile industry. Details of the conference including the full agenda are here. The conference… Read More


EDPS Monterey. Agenda Now Available

EDPS Monterey. Agenda Now Available
by Paul McLellan on 03-12-2013 at 8:13 pm

For 20 years there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey at the Monterey Beach Resort. This year it is Thursday and Friday April 18th/19th.

The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC —Read More