An Universe of Formats for IP Validation

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the number of different formats and databases the tool supports. Crossfire’s unique common data model allows different databases and formats to be cross-checked for completeness and correctness against a golden reference format or against a previous release.

There are formats to support different levels of descriptions for a design at the chip/IP, cell, transistor, or layout levels. Also there are specialized formats to describe parasitic, power, timing, test, parameter variation, and other aspects of circuits at the cell or macro levels. As the technology progresses through lower process nodes, new physical effects come into existence and they need to be modeled in many different ways. It’s not simple for designs to migrate to newer technology nodes without provisioning for newer physical effects through newer, perhaps complex models. The result is ever increasing number of design formats including but not limited to verification and power and timing specifications. Also, there are different databases from major vendors in the semiconductor industry, e.g. OpenAccess and Milky Way. Imagine this volume and diversity of data that has to be accommodated and managed in a common system like that of Crossfire. Provision to accommodate all types of formats and databases is imperative because an SoC can have IPs from multiple vendors in multiple different formats. Crossfire has a robust process of including any new format into its data model.

Fractal Technologiescommon data model for Crossfire is extensible to easily accommodate any new format. Crossfire’s first phase is to check completeness of the format for all object types including cells, pins, nets, timing arcs, and also power domains. The Crossfire compares any item that has been parsed with the equivalent item from a reference. Once a new format is proven complete, it means that its generation is well integrated into the automated characterization flow. So, any new cell or process corner added into the IP will be correctly and automatically included into the new format as well. At the SoC level, after Completeness Checks for all formats of an IP, the IP becomes ready for integration.

In the second phase, the intrinsic quality of the format is checked where characterization data such as timing and power values are checked for their correctness according to their physical aspect. Crossfire provides a rich set of quality assurance checks to dive deeper into the models provided by different formats such as trend-checks for timing and power values across process corners. For example, it can take various process corners described in the .lib files and check whether delays will indeed increase with rising substrate temperature or decrease with increasing supply voltage. The Intrinsic Quality Checks of IPs are done for final verification of the SoC before tape-out.

Recently some very important formats were added into Crossfire –

Apache Power Library (APL): This format models all power aspects of a particular cell or IP and is an important input to ANSYS’RedHawk for IR drop and reliability verification. Besides completeness check, Crossfire also checks trends for APL such as increasing currents at increasing output loads.

Unified Power Format (UPF): This is another power format promoted by Synopsys. The purpose of UPF is to describe power domains, voltages and related pins for the entire design. The power domains have to be physically separated networks in the IP design. Crossfire verifies this requirement by cross-checking UPF against SPICE netlist.

Core Test Language (CTL): This is an IEEE standard for describing the Design for Test (DFT) interfaces of a particular IP. Crossfire checks consistent naming of pins for test-control and scan-chains and their proper functionality.

Advanced On Chip Variability (AOCVM): This is an extension to Synopsys’ Liberty and is aimed at modeling the variation of cell-delays during manufacturing at lower process nodes like 14nm and 10nm. Crossfire checks for completeness and consistency of AOCVM against the available Liberty models for timing and power. It also checks for trends such as reduced variability of delays with increasing logic depth.

The Crossfire is versatile enough to include documentation formats as well. Through a PDF reader, the end-users also can parse their own proprietary datasheets into the Crossfire common data model and check the documentation for completeness. Currently, Crossfire supports over 40 different formats and databases and is able to add a new format within a few weeks time. Crossfire also provides a flexible API for users to code their proprietary checks on their IP, and those can be added on the GUI as well.

Thus Crossfire offers a very powerful environment to check IPs before their integration into an SoC and also to verify quality before the SoC tape-out. There is also a whitepaper HERE to read for more information.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com