Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More


CEO Interview: Chris Henderson of Semitracks

CEO Interview: Chris Henderson of Semitracks
by Daniel Nenni on 07-26-2017 at 7:00 am

In looking at the SemiWiki analytics over the last six years it is clear that the average age of our readers is trending down. (Yes, Google knows how old we are). The 25-35 age group now represents our largest readership and that is supported by the conferences I have attended recently. At the Design Automation Conference last month… Read More


Making photonic design more straightforward

Making photonic design more straightforward
by Don Dingee on 09-27-2016 at 4:00 pm

The arrival of optical computing has been predicted every year for the last fifteen years. As with any other technology backed by prolific research, lofty goals get dialed back as problems are identified. What emerges first is a set of use cases where the technology fits with practical, realizable implementations.

When it comes… Read More


IC Design and OpenAccess

IC Design and OpenAccess
by Daniel Payne on 03-06-2016 at 12:00 pm

EDA vendors have long used proprietary file and database formats to keep their users locked into their specific tool flow and keep any competitors from sharing in the IC design process. Along the way the actual users of EDA tools have often requested and helped to create interoperable flows so that they could mix and match multiple… Read More


An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the… Read More


Real Time Concurrent Layout Editing – It’s Possible

Real Time Concurrent Layout Editing – It’s Possible
by Pawan Fangaria on 09-03-2013 at 2:00 pm

Layout editing is a complex task, traditionally done manually by designers, and the layout design productivity largely depends on the designer’s skills and expertise. However, a good tool with features for ease of design is a must. Layout productivity has been an area of focus and various features are constantly being added in… Read More


Tanner EDA v16 OpenAccess is here!

Tanner EDA v16 OpenAccess is here!
by Daniel Nenni on 03-07-2013 at 4:00 pm

Tanner EDA is a pleasure to work with, they are big on collaboration and customers absolutely love their tools. With the Synopsys acquisition of SpringSoft, Tanner needs to step up and fill the void of the affordable Laker tools. Take a close look at their new v16 release and let me know how they are doing.

New capabilities for back-endRead More


Winner, Winner, Chicken Dinner!

Winner, Winner, Chicken Dinner!
by SStalnaker on 12-21-2012 at 8:00 pm

I have no idea if chicken was actually on the menu, but on December 12, Calibre RealTime picked up its thirdindustry award, this time the 2012 Elektra Award for Design Tools and Development Software from the European Electronics Industry. Calibre RealTime came out on top in a group full of prestigious finalists, including ByteSnap,Read More


TSMC Theater Presentation: Ciranova!

TSMC Theater Presentation: Ciranova!
by Daniel Nenni on 06-14-2012 at 9:00 pm

Ciranova presented a hierarchical custom layout flow used on several large advanced-node designs to reduce total layout time by about 50%. Ciranova itself does automated floorplanning and placement software with only limited routing; but since the first two constitute the majority of custom layout time, and strongly influence… Read More


Semiconductor Industry Standards Update 2012

Semiconductor Industry Standards Update 2012
by Daniel Nenni on 05-27-2012 at 12:11 am

Standards have been proven to reduce cost of operations, drive greater process efficiencies and offer greater opportunities for start-up companies to infuse fresh technology in the design and manufacturing of IC’s. Si2 standards have been targeted to resolve “pinch-points” in the overall semiconductor supply chain… Read More