Foolproof Your IP before it Stumbles in Higher-up Design

Foolproof Your IP before it Stumbles in Higher-up Design
by Pawan Fangaria on 08-06-2015 at 4:00 pm

SoC designs are increasingly becoming assemblies of a large number of IP blocks. A well integrated assembly can lead to a successful PPA (Power, Performance and Area) optimized design. However, it is equally important that each IP block is optimized, robust, and integrable in the design. The complexity of an IP and its integration… Read More


An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the… Read More


3D-IC Testing – A 3D perspective to SoC

3D-IC Testing – A 3D perspective to SoC
by Pawan Fangaria on 03-21-2012 at 9:30 am

In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory… Read More