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IP Development in Japan

IP Development in Japan
by Pawan Fangaria on 01-07-2016 at 12:00 pm

As semiconductor IP is growing bigger in size and more complex in providing complete solution for a particular functionality in an SoC, regions from across the world are joining to provide various types of services in the overall value-chain of IP development, verification, and its integration into SoCs.

Jedat Japan EDA Technologies is a world reputed company in the semiconductor community that provides innovative tools, technologies and services for semiconductor design solutions and its adjacent areas such as MEMS and flat-panel displays. Jedat has a large presence in Japan as well as international regions around the world through several of its partner networks, alliances and OEMs in the semiconductor domain including EDA tools, design solutions, foundries, and standards organizations.

Recently Jedat opened distributorship for Fractal’s tools in Japan region. Fractal TechnologiesCrossfire is a well known tool for quick and automated IP qualification to make sure the IP is ready for integration into an SoC. After learning about this business development between Jedat and Fractal, related to semiconductor IP in Japan, I was curious to know how IP development activities are taking place in the Japan region.

It was a great opportunity talking to Jedat executives and knowing about their perspectives on IP development activities and IP/SoC market in Japan. I talked to Mr. Kazuyuki Kawauchi san, CEO and Mr. Kenichi Tanaka san, Sales Operations Head at Jedat. Here are the highlights of our conversation –

Q: According to EDA Consortium’s quarterly reports this year, Japan region’s growth in EDA & IP revenue is almost flat to slightly negative compared to 2014 whereas Americas and Asia Pacific are showing double digit growth. How do you see the future IP market in Japan?

A: WSTS(WORLD SEMICONDUCTOR TRADE STATISTICS)announced that Japanese semiconductor market growth rate in 2015 are 2.9% in Yen base whereas -10.3% in Dollar base. WSTS also forecasts growth rate of +1.8% in 2016 and +2.0% in 2017 in Yen base. This means a gradual increase in EDA investment by Japanese semiconductor companies for next few years.

In general, as a result of structural reforms over the years in many semiconductor companies, a small number of design engineers are facing a situation where the requests from customer must be addressed within a short time span. The requests can vary in a wide range from mass production to high-complexity low-volume production. Such a change in design environment in Japanese industry is pushing for sourcing of readymade IP from internal as well as external sources. Outsourcing of design components has become important.

Q: What kind of IP development, say processor, AMS, digital, memory, or interfaces is happening in Japan and for which market segments? How about IP development in MEMS and O-S-D (Optoelectronics, Sensors, Discretes) domain there?

A: Leading semiconductor companies in Japan, which are also IDMs, must be prepared with their proprietary IPs. The fabless SoC companies need to utilize global FABs with supported IPs. With this point of view, the IP divisions in IDMs cover various areas from digital to analog including standard IPs like interfaces. The MEMS and O-S-D heavily depend on process technologies. Japan semiconductor companies, with their own processes, have been striving for differentiation in such devices. Although these devices are usually discreet devices, these will be considered for further innovation to spread as standard IP in the near future; breakthroughs in business as well as processes are needed in this case.

Q: How does Jedat fit into the overall value-chain from IP to SoC design and manufacturing of ICs?

A: Jedat provides following two solutions:

  • Analog IP design environments, including automatic migration tools which enable reduction in the overall design cycle time.
  • Support for state-of-the-art IP solution which also includes our partnership with Fractal Technologies, IC Manage Inc. (http://icmanage.com), and M31 Technology Corporation (http://www.m31tech.com).

    Q: Since Jedat has a good set of EDA tools that are part of several IP/SoC development flows, you must have felt the need of a tool like Fractal’s Crossfire. What made you start the distributorship for Fractal?

    A: We have heard from many of our customers that they are facing quality problems when integrating third party IP into their SoCs. From these experiences and working with Crossfire, we were convinced that Crossfire must be the best solution for our customers.

    Q: Did you try using Crossfire in-house and assess what kind of productivity it can provide for IP and SoC designers through automatic IP qualification?

    A: Jedat has established a design center in Kyushu, southern part of Japan last year, and started the design business in analog mixed-signal products. In the near future, Jedat plans to have its proprietary LSI products and IPs. There is no doubt, Crossfire will be of great help in maintaining quality of our IPs and design infrastructure.

    Q: Fractal already has its distribution channels in Americas, China, Taiwan, and Korea and they are doing well. Going forward, how do you see Crossfire’s distribution panning out in Japan?

    A: Jedat has already introduced Crossfire to dozens of potential Japanese customers. We recognized that each of our customers has faced serious problems with acceptance tests of new IPs, and they needed quality improvements in IP verification. Their conclusion was that Crossfire is a sure shot tool that can eliminate the bottlenecks in IP verification. Jedat is confident that Crossfire is the most effective commercial tool in IP verification and will have good business opportunity.

    Q: Any update from your existing customers or ecosystem partners on IP development, Jedat tools, and Crossfire?

    A: ROHM has realized an efficient analog IC design environment by applying the Jedat EDA tool set.

    ROHM, an analog IC giant, has delivered a lecture at the “JEDAT Solution Seminar 2015“. In that they mentioned that they could improve their design efficiency significantly by adopting Jedat’s automatic placement and routing tool for analog design. As a result, the quantity of work on designing circuit blocks was reduced by 35%, and also design quality was improved.

    This was a very intriguing conversation with Mr. Kawauchi San (on the right side in the picture) and Mr. Tanaka san. Although Japan is growing slowly in the semiconductor domain, there seems to be a bright future in that region for Semiconductor IP and SoC designs.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com