If it’s your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from what you had before, fixing only those issues that are in the way of final tape-out.
What you really don’t want are unhappy surprises in, for instance, a new Hard IP release. Suppose you requested some sleep-mode power-modeling improvements to be made as the original version showed some doubtful values for several process corners. The new IP release comes in and indeed now all process corners show consistent trends for sleep-mode power usage. But to your horror also all timing characterisation was updated, setting your design closure back by several weeks.
Were the delay modeling updates valid at all? If so, and had you known about them to begin with, the impact would have been studied on a sub-component; workarounds and synthesis adjustments would have been developed before applying a re-run of the entire design.
The problem with IP releases is often simply not knowing what is in there. In particular over time, as subsequent improvements to IP blocks are delivered, these incremental changes need be just that: incremental. Anything else carries the risk of breaking the iterative improvement synthesis cycles that take the design closer to final verification.
When new IP is received an incoming inspection needs to be performed. Part of this task is to verify that the IP is internally consistent and complete and meets the quality requirements agreed with the IP supplier. This task is typically done by Fractal Crossfire™, the industry-standard tool for IP qualification. If the IP release is intended to replace a previous version in a design, IPdelta™ must be used on top of Crossfire ™ to bring out the changes introduced in the new version.
The objective of IPdelta™ is to inventory all aspects in which one IP revision may differ from the next. Every database and file-format supplied is compared and deltas are reported for every relevant category of design data. This includes basic elements like cells and terminals but extends to delay-, power- and noise- arcs, their conditions and associated characterization data. Also physical layout (LEF, OASIS, OA, MilkyWay) is covered, as are schematics, netlists, synthesis properties and functional models.
Fractal Technologies is a privately held company with offices in San Jose, California and Eindhoven, the Netherlands. The company was founded by a small group of highly recognized EDA professionals. Fractal Technologies is dedicated to provide high quality solutions and support to enable their Customers to validate the quality of internal and external IP’s and Libraries. Thanks to our validation solutions, Fractal Technologies maximize value for its Customers either at the Sign Off stage, for incoming inspection or on a daily basis within the Design Flow process. Fractal Technologies goal is to become the de facto IP & Library Validation Solutions Provider of reference for the Semiconductors Industry, while staying independent to keep its intrinsic value by delivering comprehensive, easy to use and flexible products.