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Enabling Next Generation Silicon In Package Products

Enabling Next Generation Silicon In Package Products
by Kalar Rajendiran on 04-15-2021 at 10:00 am
Categories: Alphawave Semi, Events, IP

System on Package Motivation AlphaWave IP

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been categorized into eight different subject matter tracks. The tracks were Advanced Packaging Solution and Chiplet, Analog and Memory Blocks, Design and Verification, Interface IP, Security Solutions, Automotive IP and SoC, Video IP and High-Performance Computing.

Semiconductor Packaging as a technology has garnered lot of investment and attention for many years now. We have had various innovations over the years including flip-chip, silicon interposer, 2.5D, 3D, chip scale packaging and wafer level packaging. Many of these advances were driven by the need to overcome device performance limitations, signal-integrity issues, form-factor constraints and/or simply market acceptance price points. So, the “advanced packaging solution and chiplet” track piqued my interest and I listened in on some of the presentations.

One of the presentations I listened to was titled “Enabling Next Generation Silicon In Package Products” and was presented by Tony Pialis, the CEO of Alphawave IP, Inc.

There is a long history of successful system-in-a-package (SiP) products launched by different companies. One reason for going the SiP route is faster time to market (TTM). By mixing and matching IP that pre-exist in different process technologies, the time, effort and cost of having to port the different IP blocks to the same process technology is avoided. System-in-a-package interchangeably referred to as silicon-in-package is not a new concept.

So, why was Tony’s presentation under the Advanced Packaging track? This blog addresses that question through salient points gathered from Tony’s talk. For complete details, please register and listen to Tony’s entire talk.

Next generation products are expected to see broader and faster adoption of SiP. As sub-10nm process node becomes main stream, two strong reasons for SiP adoption come into play (see Figure 1). The first reason: System-on-a-chip (SoC) development cost crossing the $500M mark. That is a 20X increase compared to the cost of developing an SoC in 65nm process node. The second reason revolves around die yield and number of good dies per wafer. The yield rate is better for smaller dies. Here in lies the opportunity to benefit economically, if all technical challenges can be overcome.

Figure 1: Opportunity from an Economic Perspective

 

Technical Challenges:

Achieving the economic benefits requires disintegrating an SoC die into smaller dies. In this context, these smaller dies are being termed chiplets. Simplistic definition of a chiplet: a die that holds a functional circuit block. But this approach of partitioning into chiplets introduces many challenges. A number of nanometer pitch wires that were on-chip now turn into package-level interconnects, thereby introducing signal integrity issues. longer latencies, increased power and test complexities.

Technology Solutions:

The good news is that manufacturing capabilities in the form of silicon interposer, through-silicon-vias and chip scale packaging technologies already exist to enable chiplets integration. The focus is now on chiplet interfaces to eliminate the signal integrity, latency and power issues. At a basic level, partitioning of an SoC leads to chiplets that are primarily logic bound, memory bound or I/O bound. The chiplet type determines what type of interface makes sense and what interface standards are available/supported.

Parallel interface implementations such as the Bunch of Wires (BoW) interface which is an Open Domain-Specific Architecture (ODSA) sub-committee supported standard, and the Advanced Interface Bus (AIB) interface which is an Intel/DARPA supported standard are well suited for use with logic bound chiplets.

The High Bandwidth Memory (HBM) interface standard, which is well established and in wide use is more suited for memory bound chiplets.

Serial interface implementations such as the XSR (extra short reach) and the USR (ultra short reach) interfaces are well suited for use with I/O bound chiplets.

In his presentation, Tony discusses lot of details in terms of supported speeds, latencies, power, bandwidth, etc., for each of these interface types. He delves deep into Alphawave IP’s DieCORE 112Gbps XSR interface IP and discusses ways of managing bit error rate (BER) performance.

If interested in benefiting from a chiplets implementation approach, I recommend you register and listen to Tony’s entire talk and then discuss with Alphawave IP on ways to leverage their different IP offerings for developing your products.

Also Read:

CEO Interview: Tony Pialis of Alphawave IP

Alphawave IP and the Evolution of the ASIC Business

Alphawave IP is Enabling 224Gbps Serial Links with DSP

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Low Energy SoCs with Near Threshold Voltage

Low Energy SoCs with Near Threshold Voltage
by Tom Simon on 04-15-2021 at 6:00 am
Categories: IP, Minima Processor

Low Energy Efficiency

There is an important difference between low power and low energy in SOC design. Low power focuses on instantaneous power consumption. This is frequently done to deal with cooling and heat dissipation issues. Of course, it serves as a prerequisite for low energy design, which seeks to reduce overall power consumption over time. Low energy is desired when energy is limited, such as in a battery, photovoltaic or other energy harvester. Low energy systems either have to get a certain amount of processing done with the available energy supply or they may have to preserve system operating life.

One of the most obvious techniques for reducing energy consumption is to reduce the operating voltage of the system. This can reduce dynamic energy consumption proportionally to the square of the voltage. Operating at or near threshold voltages offers big savings in energy consumption. So why not deploy it widely?

Low Energy Efficiency

In a video recording of a DAC presentation by Minima Processor’s CTO Lauri Koskinen titled “Near Threshold Voltage: A Much Needed Reality or Risky Dream?” the pros and cons of near threshold operation are discussed. Without giving too much away, it is clear that near threshold voltage operation is an important arrow in the quiver of things that can be done to reduce system energy consumption. However, several specialized techniques need to be employed to maintain system performance and yield in chips intending to take advantage of this approach.

Lauri points out in his presentation that there is a minimum energy point for devices that is very close to the threshold voltage. If you overlay the maximum operating frequency (Fmax) on this, it is evident that for many applications the work per unit of energy can be optimized. Yet, this can be at a point where variation causes extreme shifts in device performance. Lauri points to evidence showing that subthreshold operation can cause 20X greater performance deltas due to random variation than operation at higher voltages.

Lauri asserts that near threshold operation offers great benefits without the difficulties of subthreshold, but still needs specialized techniques to make it commercially effective. Lauri points out that with specialized libraries and the use of advanced voltage scaling (AVS) that good results have been achieved. He presents several near threshold chips that have been designed over the years using standard design flows. They range from 180nm down to 14nm, all having very impressive low energy consumption.

He wraps up by reviewing the key success factors that will provide a path forward to low energy SOCs that can be used in products that require long battery life or operating times with alternative power sources. AVS and dynamic voltage and frequency scaling (DVFS) are first on his list. The latest EDA tools have capabilities that will support this type of design. He points out that there will have to be additional types of test methodologies to handle these designs. Beyond the methods above, allowing higher levels of granularity and intelligence in creating voltage islands and power domains is a powerful technique to ensure overall system performance while being miserly with energy consumption.

It is becoming more common for wireless devices to offer 10 year battery life. For instance, we see this in household lighting applications for remote wireless switches. Industrial applications and other uses where battery replacement or provisioning will create extra costs will be candidates for the most aggressive possible energy savings. Also, applications like earbuds call for maximizing useful life. We can expect to see more advanced and intelligent approaches to solving these challenges. If you want to view the entire DAC presentation given by Minima’s Lauri Koskinen it can be viewed here on their website.

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Global Variation and Its Impact on Time-to-Market for Designs

Global Variation and Its Impact on Time-to-Market for Designs
by umangdoshi on 04-14-2021 at 2:00 pm
Categories: EDA, Synopsys

Impact of Global Variation on Delay

We have come a long way from the days of limited and manageable characterization databases with fewer views and smaller library sizes. The technologies we are headed towards pushing characterization to its limits with special modeling for variation, aging and reliability all on a single process, voltage and temperature (PVT). Additionally there is a requirement to generate basic nominal timing/noise/power views as well as more complex variation views.

With the advancement in technology and the push towards smaller nodes from 7nm down to 3nm, the designs are expected to work under different modes, with possibly different clock frequencies along with a range of global variations. Thus, the designs have to achieve signoff closure for timing and power across an enormous number of PVT corners. Characterizing these huge number of PVT corners, library teams across the industry face further challenges like high simulation turnaround time, database disk-space, license server overloads and hardware costs. All of these result in overall impacting adversely the time-to-market delivery of designs in a cost-effective manner.

Characterizing multiple PVT corners can be done using multiple methodologies. One such is brute-force method, where using many compute resources runs all possible PVT corners required in parallel and thus reduces the overall turn-around time (TAT). Another method is to characterize timing data for nominal while scaling the Liberty Variation Format (LVF) data, which is about 60-70% of the overall runtime for library characterization, thus achieving 2-4X faster TAT. Both these methods have their pros and cons -while the compute cost to generate all libraries in parallel is significantly higher, the libraries are very accurate, whereas for scaled LVF data the compute cost is lower, but with a possible sacrifice in accuracy.

Not only does Synopsys offer a feature for scaling LVF data to generate SmartLVF (as illustrated in Figure 2) libraries for multiple PVT corners, we have developed an advanced ML-based scaling feature called SmartScaling which fits right into this requirement space to provide the much-required relief for designers. SmartScaling for multi-PVT characterization enables designers to create interpolated Liberty models at zero cost while maintaining signoff accuracy. This significantly reduces overall runtime and alleviates concerns of database management thus providing the most accurate, cost-efficient solution.

With an easy-to-use UI to accept user-defined anchor libraries over a range of conditions, SmartScaling can quickly create libraries at other corners as chosen by the user. While this is the most basic usage, it also offers further advantages to adaptively select anchor corners to get best scaling accuracy, accept user-controlled custom indices, do some cross-PVT trend checks and then some more!

Designer’s needs may vary – from simply creating structurally consistent placeholder Libs for end- to-end flow flush to producing accurate intermediate PVT’s for signoff – and the solution is SmartScaling.

Summary

Multi-PVT characterization has become necessary to generate libraries that include model variations, aging and reliability data at the most advanced nodes. This imposes an increased demand for computing resources needed for characterization which increases time-to-market and overall cost for the design. Synopsys’s SmartScaling for multi-PVT characterization improves the runtime significantly to provide over 3X increase in efficiency and reduce overall cost.

With latest innovation in Synopsys’s library characterization, achieve faster and more accurate variation models with the goal of generating PrimeTime® signoff quality libraries. Learn more about the close collaboration and integration between various signoff products at www.synopsys.com/signoff

Also Read:

VC Formal SIG Virtually Conferences in Europe

Key Requirements for Effective SoC Verification Management

Techniques and Tools for Accelerating Low Power Design Simulations

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Semiconductors, the E-waste Problem, and a Pathway for a Solution

Semiconductors, the E-waste Problem, and a Pathway for a Solution
by rahulrazdan on 04-14-2021 at 10:00 am
Categories: Semiconductor Services

ewaste

Semiconductors have been central to the information revolution which is reshaping society. The modern world would not exist without this critical resource.  Further, semiconductors are central to many sustainability solutions such as the enablement of smart infrastructure, electrification, and virtualization. One of the consequences of this tremendous growth is the ever increasing generation of e-waste.  How big is this problem ?   Is there a way to solve this problem ?  Let’s examine the situation. 

What is the nature of the e-waste problem ?   

E-Waste Dump in Agbogbloshie Ghana

E-waste is the result of electronic products which have outlived their usefulness.  Waste electronics contain several toxic additives or hazardous substances  such as mercury, brominated flame retardants (BFR), chlorofluorocarbons (CFCs), or hydrochlorofluorocarbons (HCFCs). Without safe disposal,  this waste stream poses significant risks to the environment and to human health.  In fact, the toxic nature of E-waste has caused countries such as China to stop accepting e-waste shipments from the west, and prompted this Atlantic article to ponder “ Is This the End of Recycling?”    Other locations for e-waste disposal have included third-world countries such as Ghana (Video Story)  and Pakistan (Video Story). The e-waste problem is  increasingly becoming visible in the popular consciousness. Recent articles include:

  1. The World Has an E-Waste Problem (Time)
  2. We dissected nearly 100 devices to study e-waste. What we found is alarming (fast company)
  3. News by Numbers: India’s mountain of e-waste (Forbes)

How did we get here ?

Of course,  the starting point is the explosion of consumer devices which are reshaping society.  Consumer devices are of particular concern because of the both high volume and short lifetime of use.  After their end of useful life, electronic products turn into e-waste and follow a backwards deconstruction flow as shown in the figure below.   The fundamentals of the flow are to use a managed process to salvage value when economically appropriate, and if value cannot be found, the product results in a landfill. The large steps are:   

  1. Product Collection:  A percentage of e-waste (only 35% in US)  is collected in “official” e-waste where it goes through a reclamation process. The rest end-up in landfills.  
  2. Disassembly:  Products are disassembled into major components if the cost of disassembly is viable. Otherwise the product is shredded.  As an example, Apple has built robots  such as daisy which employs mass volume techniques to reduce the costs dramatically.
  3. Chip Reuse:  Valuable chips can be extracted and reused based on the economics of doing so (extraction, secondary markets).  Unfortunately, the secondary markets for these chips are dark, and prone to issues of counterfeiting.  In some cases, these can even lead to national security issues.
  4. Materials Extraction:  Finally, valuable elements such as gold/silver can be extracted in a chemical deconstruction process.

In the best of circumstances, these processes are done in safe working conditions, but as the video stories above show, these processes often occur in third-world countries under less than ideal conditions. 

What is the pathway to a solution ?

The electronics industry has spent countless billions on research to build fantastic products at incredibly low costs.   Today, for the most part, when a product moves into the e-waste bucket, it’s value moves from an incredibly engineered machine down to its base value in elemental materials. This is akin to viewing the human body for its mineral value.  

A very critical issue is the ability to capture value at higher levels of reuse because that changes the economic dynamics of collection and disposal to a landfill. Today, the research investment in the backwards flow is remarkably lacking.  Research and a minor amount of industry wide standards cooperation along a number of vectors can change the economics of e-waste significantly.  These vectors include:

 

  1. Mechanical Disassembly:  Mechanical disassembly is a key cost which must be managed. Robotics based high throughput, low cost mechanical disassembly is critical to addressing these costs. With a sufficiently efficient process, the economics of recycling become enabled. Research:   Novel design-for-disassembly techniques which enable high volume, low cost disassembly while not compromising product performance are required.  Standards/Industry Cooperation:  Ideally, any robotics based disassembly techniques are provided in open standards which enable the e-waste eco-system.
  2. Board and Subsystem Reuse:  If the whole product cannot be reused, research in productive ways to reuse natural subsystems is desirable.  Research:  Most dominant consumer devices contain more powerful capability than the Apollo space computers. This capability should have a value which is useful for other domains.  Computer architecture research which finds valuable repurposing the major consumer platforms (laptops, mobile phones, tablets, etc) can significantly shift the economics of reuse. Standards/Industry Cooperation:  To fruitfully use a board, the first step is to validate its correctness, so standards for testing the boards with associated test suites are invaluable. OEMs may even consider a “Certified Board” construct to enable this process.
  3. Chip Reuse:  Safe and scaled manufacturing methods for board disassembly can lower the costs to obtain chips. Once the chip is available, the reuse flow is well understood, and this process occurs today. However, the chips themselves are in dark secondary markets. Standards/Industry Cooperation: To fruitfully use these chips, Semiconductor companies should consider a “Certified Chip”  construct where they are actively engaged in the validation process. 
  4. Materials Extraction and Disposal:   Today, various chemical techniques are used to harvest key elements from e-waste.  Research:  Continued research on lowering the cost of extraction and extracting more value in a safe manner can lead to positive consequences. A recent example is the work of ex-Tesla employees with Redwood Materials to extract lithium from batteries.  Standards/Industry Cooperation: Standards on the major processes for extraction and disposal of these materials is likely to lead to lowering of costs and higher levels of reuse.

Why now ?

Good citizenship and the potential for building profitable businesses are good reasons for the electronics industry to pursue solving the e-waste problem.  This work can certainly be part of any ESG reporting for the investment community. However, an urgency to this process may well be to address the rise of the coming regulatory response.  Significant activity to date includes:

  1. Europe:  In the european Union,  the fundamental concepts of circular material flows and “right to repair”  are gaining traction. 
  2. US States:  In the US, over 25 states have enacted electronics waste laws. 

Recently, some industry wide movement has happened recently with the World Economic Forum’s announcement of the Circular Electronics Partnership (CEP), and there has been some investment from the US Government in e-waste research with entities such as the Re-Made institute ($70M).   However, to make progress,  it is very likely that the traditional standards bodies such as CTA and SIA will have to get involved.  In addition, the traditional funders of the forward flow research such as Semiconductor Research Consortium (SRC), NSF, and perhaps even DoD will need to participate.   Overall, Industry focus on standardization, market formation, and reuse research, can significantly impact e-waste.

Note 1:  There has been some churn on the e-waste issue direction in the popular media. The article “Is E-Waste Declining ?     The rest of the story “ addresses this topic.

Note 2: The Global E-waste Monitor 2020 report  by  Vanessa Forti, Cornelis Peter Baldé, Ruediger Kuehr, and Garam Bel  from the United Nations University provides a decent background to this topic.  

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Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio

Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio
by Bernard Murphy on 04-14-2021 at 6:00 am
Categories: EDA, Siemens EDA

Siemens Hardware assisted Verification platform launch graphic 2 32521 min

Siemens EDA’s Veloce emulation products are long-established and worthy contenders in any emulation smack-down. But there was always a hole in the complete acceleration story. Where was the FPGA prototyper? Current practice requires emulation for fast simulation with hardware debug, plus prototyping for faster simulation for software testing and debug. For Siemens that prototyping hole is now filled. They now offer the complete range: hardware acceleration platforms for enterprise-level emulation, enterprise-level prototyping and desktop prototyping. Good news all round, because ESDA is now showing that spend on hardware acceleration solutions is overtaking spend on conventional simulation.

Upgraded emulation

This announcement is part of a broader announcement. The emulator, Veloce Strato, now has a higher capacity/performance sibling – Veloce Strato+. They’ve made multiple improvements for this system. First they’ve added the HYCON platform to co-model between the emulator and a virtual platform. You can run large software stacks on a virtual platform at near real-time speeds, jumping to the emulator (at lower speeds) only as needed.

Second, they have upgraded the compile flow to take advantage of hierarchy and distributed processing wherever possible. Here they take advantage of multi-CPU processors to accelerate throughput. Total verification turn-time is as much a function of compile time as much as run-time. A fact that comes home very quickly to designers dealing with frequent RTL drops.

New chip goes 2.5D

And third, Siemens EDA have spun a new accelerator chip, Crystal3+. Here they took the Strato board architecture and pushed the memory and processor into a 2.5D package. Increasing performance per processor (interposer delays to memory rather than board delays) and increasing the number of chips they can put on a board from 16 to 24. Interestingly, the chassis remains the same. You can simply pull out the Strato boards and replace them with Strato+ boards. AMD (Alex Starr) has been working with Siemens on this platform and has provided an endorsement. They’ve also endorsed models for the 2nd and 3rd-gen EPYC processors to work with this solution.

The Primo and ProFPGA prototypers

This is the big news for me. Primo is a full function prototyper with a datacenter footprint, with all the required features. ICE and virtual prototyping support, streaming to memory or host, multi-user support, down to one FPGA granularity. It shares a common compile front-end with Strato+ (as does the ProFPGA solution), minimizing turn-time to jump between platforms. And it also provides a common interface to the virtual modeling platform. Very neat. You can setup a complete verification environment, virtualized CPUs to RTL modeling to ICE/virtualized testbench and swap between emulation, enterprise prototyping and desktop prototyping.

Primo scales to 320 FPGAs and is based on the latest Ultrascale+ device from Xilinx. Arm has endorsed Veloce Primo.

Desktop prototyping

Veloce ProFPGA is for desktop prototyping, developed in partnership with ProFPGA. Because that’s what you need when you want to work on a real (not virtualized) testbench, plugging into real traffic generators, consumers and monitors. You can scale from one uno board to 5 quad boards, with choices of Intel Stratix 10GX10M or Xilinx XCVU19P FPGAs.

Jean-Marie Brunet (Sr. Dir Marketing and more at Siemens EDA) mentioned that they also provide full visibility to signal states in both prototyping platforms, leveraging signal reconstruction technology from Veloce software.

You can learn more about the release HERE.

Also Read:

Formal for Post-Silicon Bug Hunting? Makes perfect sense

Library Characterization: A Siemens Cloud Solution using AWS

Smarter Product Lifecycle Management for Semiconductors

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Certitude: Tool that can help to catch DV Environment Gaps

Certitude: Tool that can help to catch DV Environment Gaps
by admin on 04-13-2021 at 2:00 pm
Categories: eInfochips, Semiconductor Services
1 Comment

Certitude 9

Design verification (DV) is still one of the biggest challenges in the ASIC based product world. In last two decades, we have seen many changes in terms of HVLs and methodologies used for design verification. System Verilog is the most popular HVL these days and UVM is the most popular verification methodology.

Even after such an advancement in HVLs and DV methodologies, quality of actual Design Verification is still largely dependent on DV engineer’s verification skills. Due to human intervention, there are chances of design bugs escape in ultimate design. Such design bugs, fall in critical bug category, leads to chip respin which can be very expensive and above all affects the “time to market” of the product which is very critical for a product company.

To avoid such possible design bug escapes and to minimize the risk, chip design companies adopt different tools in addition to actual EDA simulation tools used for verification. This includes formal verification tools, emulation tools and more. The key goal is same and that is to make sure final design that is taped out is design bug free.

Sometimes, Certitude, a tool from EDA tool company Synopsys, is used to measure verification environment strength. The fundamental usage of this tool is to catch DV environment holes that can lead to design bug escape. This paper talks about how the Certitude tool works, how can it help in catching DV environment gaps, it’s pros and cons based on our own experience, where it is used on a complex mix signal ASIC design.

How Certitude Works?

Certitude introduces bugs in specified RTL design modules which are known as “Faults”. It then runs specified (in certitude_testcases.cer) tests using existing verification environment (VE) and checks whether the VE detects the injected fault or not. At least one test is expected to fail for one fault at time due to one or more failing symptoms mentioned below,

  • Data checker failure that includes data integrity check OR status check
  • SystemVerilog Assertion failures
  • Simulation timeout reached.

Certitude mainly divides “Faults” into few class categories. But the most important fault classes that should be exercised and analyzed are as below.

Top Outputs Connectivity:

This category of fault inserts faults on the output signals of top design module (specified in certitude_config.cer).

For an output port of a top module, Certitude updates RTL design by injecting StuckAt1, Stuckat0 and Negated faults. This means actual output port is driven by “1”, “0” OR “inverted” value considering the fault.

See in below top module of a design, for an output port at line 16, certitude injects three different faults,

Top Module of designs specified.

OutputPortStuckAt0 fault (Fault ID 691)

As shown in below snippet, actual output port is commented and internally driven to “0” by tool.

OutputPortStuckAt1 fault (Fault ID 692)

As shown in below snippet, actual output port is commented and internally driven to “1” by tool.

OutputPortNegated fault (Fault ID 693)

As shown in below snippet, actual output port is commented and internally driven to inverted value by tool.

ResetConditionTrue:

This fault class considers reset related signals, which are used to set internal signals, status, and error signals to their Init (PowerOnReset) values.

Example, in below snippet, this category of fault injects three different faults for line 67.

ConditionFalse :

It replaces line 67 with, if(1’b0) begin

ConditionTrue:

It replaces line 67 with, if(1’b1) begin

NegatedCondition:

It replaces line 67 with, if (!(i_async_rst_x) begin

InternalConnectivity:

This fault class considers signals to inject faults to the input of design sub modules.

Below snippet shows a submodule is instantiated in a module and tool has identified 3 faults for port connection at line 503.

The faults are,

InputPortConnectionStuckAt0 (Fault ID 1100)

It replaces line 503 with,

.i_ch1**_x (‘h0) begin

InputPortConnectionStuckAt1 (Fault ID 1101)

It replaces line 503 with,

.i_ch1**_x (‘h1) begin

InputPortConnectionNegated (Fault ID 1102)

It replaces line 503 with,

.i_ch1**_x (~(ch1_**_x[27:0])) begin

Brief on Certitudes Phases:

Certitude runs in the phases listed below. There are options to selectively run one or all pf these phases.

Model Phase:

Certitude analyzes the RTL design and collects all required details about design modules to consider, their outputs, inputs and wires to be considered for different types of faults insertion. This phase finds all possible faults to be considered to exercise design in next phases. Design modules to consider for certitude run can be added in certitude_hdl_files.cer

Activate Phase:

Before starting this phase, one needs create the test suite (tests that DV engineers think can effectively exercise the design modules), which tool will use to exercise the selected RTL design modules. Certitude runs the regression using this test suite and checks that signals on which certitude is going to insert the faults toggle or not. This mean it qualifies the test suite against faults to be inserted.  If the fault related signals toggles for a test, then that test is considered as qualified test for that fault and is considered in next detect phase.

Based on the report out of this phase, one needs to update the test suite and run this phase again multiple times to identify more qualifying tests for all “Non Activated” faults. As a final result of this phase, we have test suite that qualifies all faults that tool has identified. There are options to run this phase incrementally so that for each iteration it only considers newly added test to qualify “Non Activated” faults.

Detect Phase:

Certitude injects faults on each qualified signal one by one and runs the regression. At end of the regression, it provides us the summary report how many faults once injected are detected by verification environment. The expectation is at least one test to fail for each fault. The report gives details as,

Detected faults:

Details on all the faults which are detected by the existing verification environment when certitude insert the faults. This number represents faults for which we have some failures. VE can detect design issue for these faults.

Non-detected faults:

Details about faults which are not detected by the existing verification environment when certitude insert the faults.  This means, for these faults, none of the test failed. It means VE missed to catch the design bug inserted for all such non-detected faults.

Non-Propagated faults:

These are the faults which though activated, does not change the ultimate design simulation result. This means, final output remains the same with and without the fault.

This can happen when fault propagated the effect up to certain hierarchy but not all the way that enables change in final behavior.

Looking at detect phase report, one needs to analyze the Non-detected and Non-propagated faults. The DV engineer has to look at each fault and decides why it remained Non Detected or Non propagated based on the reference specs. Corrective actions can be taken based on analysis and that includes,

  1. New test needs to be added in the existing test suite provided to certitude. This can be an existing test OR to be created brand new.
  2. There are chances that some faults may result in some illegal scenario considering design reference specs. DV engineer can check with the designer for such fault and can decide to exclude it. There are options to disable specific fault(s) once required approval is received from concern person.
  3. We may end up updating existing checkers to catch such faults.

In case we update any assertion or checker, which is considered as DV update, we have to run Model + Activate + Detect phase again from scratch. If it is just an addition to the test suite then we can just run incremental Activate + Detect phase. This will not exercise existing database for faults already detected.

Below are some basic examples of possible scenarios which certitude can help to catch. We can say them as “DV holes or DV gaps”.

Address flip for memory:

If Memory controller’s output address bits are swapped due to fault insertion for both write and read accesses, then it won’t be detected using normal write and read operations.

To detect this, test with front-door write and backdoor read scenario has to be present in DV test suites. If this test scenario is not present, then Certitude’s “OutputPortNegated” fault remains undetected. Certitude can help to identify such faults if any.

Assertion at sub-module hierarchy:

If SV assertion is written using sub-module’s I/O ports where Certitude inserts faults (StuckAt-1, StuckAt-0, Negated fault), then such faults remains undetected. This is because assertion uses same faulty value to predict/check design behavior.

To catch such faults, assertion has to be written using higher-level module’s port or using some glue logic that derives final values to be driven at the submodule’s port boundary. For example, such logic can include data bus writes OR read requests decoding to derive final control signals to use in assertion rather than using sub module’s i/o ports.

Assertion that checks 1’b1 OR 1’b0 on event:

If SV assertions are coded to check that value on some port is driven 1’b1 OR 1’b0 on some condition and if Certitude inserts faults (StuckAt0 OR StuckAt1) that matches assertion expectation, then it won’t result in any failure. DV engineers can find such coding issues “always PASS” using Certitude that may leads to some interesting scenarios.

Reports and details each report provides:
Below snippets depict certitude results report after the detect phase. Tool allows access to such reports while detect phase is ongoing without affecting simulations running.

Report Summary:

Below snippet gives overall status of the detect phase.

Report Summary:

Below snippet gives overall status of the detect phase.

Where,

Faults Disabled By Certitude is for faults disabled by certitude based on configuration option settings.

Faults Disabled by User is for user disabled faults based on analysis or discussion with designer.

Faults Dropped are faults that Certitude drops if it is dependent on some other non-detected or non-propagated fault in the same area. For example, if case statement is not detected then tool drops faults on all statements under it

Per Fault Class Summary for a design module:

It shows details related to the faults exercised during detect phase based per Fault Class of a module. So far, this paper has talked about top 3 Fault Class types and they are the one DV engineers should analyze with highest priority compare to others. Reports shows how many faults are detected, non-detected, non-propagated etc for a design module.

Per Design Modules overall status:

Below snippet shows module-based fault classification. Each module participating in Certitude run and their faults status.

The runtime of the detect phase mainly depends on,

  1. Number of tests added in Certitude test suite to activate each fault. It is preferred that user identifies the key tests in such a manner which can hit maximum logic in the design. This will help to run a smaller number of tests thus saving on simulation license as well as certitude run time
  2. Runtime of each test added. Longer the simulation runtime result in increases the detect phase run time
  3. Number of faults to be exercised. Mode design modules means more faults to exercise and hence more tests required to hit related functional scenarios.

Summary of using Certitude in a project:

  • Helps in identifying corner cases which are hard to think about.
  • Design module selection and other options allow Certitude to run effectively on key design modules and help to gain confidence on Design Verification done
  • It is advisable to run Certitude in the later stage of a project, when most of the DV work is done and once thorough design verification is complete, but this affects the project deadline.
  • Some faults are not legal with respect to design spec but still if they fall in Non-Detected or Non-Activated category, one has to spend time closing them, which is time consuming or  “Return over efforts” may not add much value.
  • Some faults may not lead to use case scenarios of final product but still one may end up spending time to close them.
  • Depending of design complexity, tool identifies large number of faults and to run them using certitude is time consuming and needs large number of simulation licenses. This adds an additional cost to the project.

Conclusion:

As described, based on design complexity, third party proven design IPs vs key custom design blocks used in an SoC, one can go with Certitude tool and run it on entire design or on selected design modules to gain more confidence on quality of the design verification done on those design modules. Using this tool, one may or may not find any bugs in design or DV gaps based on how thoroughly the DV is done but it can surely help in gaining DV confidence. Sometimes it leads to uncover some corner case scenarios, which are hard to think about and are missed to cover in verification plan. Based on design specs and use case scenarios, DV engineers can decide on whether to add those scenarios or can get waiver from design leads to drop them.

To know more please see the Synopsys webinar or contact our experts.

Authors-
Manzil Shah – Technical Manager, eInfochips-An Arrow Company
Bipin Patel – Member Technical Staff – (Level 2), eInfochips-An Arrow Company
Vishal Mistry – Member Technical Staff – (Level 2), eInfochips-An Arrow Company
Shashank Mistry – Senior Engineer – (Level 2), eInfochips-An Arrow Company
Ronak Bhatt – Engineer, eInfochips-An Arrow Company

Also read:

Understanding BLE Beacons and their Applications

Digital Filters for Audio Equalizer Design

Sign Off Design Challenges at Cutting Edge Technologies

Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II

 

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The Juggernaut Continues as ESD Alliance Reports Record Revenue Growth for Q4 2020

The Juggernaut Continues as ESD Alliance Reports Record Revenue Growth for Q4 2020
by Mike Gianfagna on 04-13-2021 at 10:00 am
Categories: ESD Alliance, Semiconductor Services, Wally Rhines

The Juggernaut Continues as ESD Alliance Reports Record Revenue Growth for Q4 2020
Marvel’s Juggernaut

Apologies for the slightly hyperbolic title of this post. Webster defines Juggernaut as “a massive inexorable force, campaign, movement, or object that crushes whatever is in its path.”  Marvel Comic fans will recall the term also refers to a superhero nemesis. But I digress. The ESD Alliance recently announced its Q4 2020 Electronic Design Market Data Report.   I covered the Q3 2020 report here. That was very upbeat news. Something that seemed hard to top. But that’s exactly what happened in Q4. Stronger and record-setting results. Read on to find out how the juggernaut continues as ESD Alliance reports record revenue growth for Q4 2020.

Let’s start with some basic statistics. Revenue for EDA, IP and services grew 15.4 percent in Q4 2020 when compared to Q4 2019. That same growth comparison for Q3 2020 was 15 percent. Overall revenue increased by over $1 billion in 2020, which is a new milestone for the industry. This is only the fourth time since 2011 that year-over-year growth exceeded 15%. The four-quarter moving average, that compares the most recent four quarters to the prior four quarters, rose by 11.6%, which is the highest annual growth since 2011 and the second highest in the last 14 years. The companies tracked in the report employed 48,478 people in Q4 2020, a 6.7% increase over the Q4 2019 headcount of 45,416 and up 3% compared to Q3 2020. Wondering what happened to all that pandemic gloom and doom? Me, too. These results are in the rare air regarding positive achievement.

I was able to catch up with Wally Rhines to get some of the back story on all this good news. Wally is the executive sponsor of the SEMI Electronic Design Market Data report.  We started by remembering our prior discussion on the Q3 results. Those were really good, and Wally did confirm they’re now even better. We talked about what’s driving all this good news. The many new system companies who have realized the significant benefits that custom silicon delivers are certainly helping to raise the water level for all. Wally referred to the customization phase of Makimoto’s Wave, a characterization of innovation cycles by Tsugio Makimoto, former CEO of Hitachi Semiconductor. You can learn more about this phenomenon here.

The bottom line is that more custom design is being deployed to achieve the required PPA for next generation products, and that’s good news for EDA and IP. Here is a summary of revenue by application category for Q4 2020:

  • CAE revenue increased 9.4% to $956.9 million compared to Q4 2019. The four-quarter CAE moving average also increased 9.4%
  • IC Physical Design and Verification revenue increased 36.6% to $637.1 million compared to Q4 2019. The four-quarter moving average for the category rose 12.3%
  • Printed Circuit Board and Multi-Chip Module (PCB and MCM) revenue decreased 0.8% to $292.9 million compared to Q4 2019. The four-quarter moving average for PCB and MCM increased 4.3%
  • SIP revenue increased 16.9% to $1,052.9 million compared to Q4 2019. The four-quarter SIP moving average grew 17.1%
  • Services revenue increased 2.2% to $91.6 million compared to Q4 2019. The four-quarter Services moving average decreased 2.4%

Architectures are getting more complex and chip/system-in-package designs are getting larger, which explains the dramatic growth of physical design & verification as well as semiconductor IP. Overall, Wally saw no reason for the current wave of innovation to slow down. I completely agree. As we’ve all endured a year with a lot of bad news, you can take comfort in knowing there is good news for EDA and IP and the world-changing innovation it drives. I would say Tsugio Makimoto got it right, so take comfort – the juggernaut continues as ESD Alliance reports record revenue growth for Q4 2020.

Also read:

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

EDA Appears to Have COVID Immunity – ESD Alliance Reports Strong Q2 2020

UPDATE: Everybody Loves a Winner

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Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!

Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!
by Eric Esteve on 04-13-2021 at 6:00 am
Categories: IP, IPnest, Semiconductor Services

Table IP vendors 2021

Design IP Sales Grew 16.7% in 2020, to reach $4.6B and this is the best growth since year 2000!

The main trends shaking the Design IP in 2020 are very positive for the Top 3 IP vendors, each of them growing more than the market and confirm the importance of the wired interface IP market, aligned with the data-centric application, hyperscalar, datacenter, networking or IA.

ARM is again a solid #1, with more than 40% market share, and, important to notice, 17.4% growth, slightly more than the IP market. Does this growth rate indicate that ARM’s trouble with Chinese management has been cleared, or simply shows that ARM’s sales behavior is online with the IP market? It’s difficult to answer, but ARM’s IP royalty sales grow by 16% and IP license sales by 19.9%.

This high growth in IP license sales is incredibly positive for the future. It indicates that, if RISC-V still generates strong interest and communication, the industry accepts to pay license fee to benefit from ARM products, and ARM has released enough new products to attract customers in high-end markets, CPU and GPU for smartphone, CPU v9 for AI, security and computing and more. ARM being the undisputed CPU and GPU IP leader for application processor for smartphone, royalty sales have reached a maximum for these applications. The next big markets to target are automotive and datacenter or AI if we consider that IoT or MCU are real, but too fragmented to represent the same large opportunities. It took some time to ARM’s management to come to this conclusion, that they did when transferring IoT ARM to Softbank. There is certainly room for significant license and royalty sales increase if ARM can be successful when targeting these automotive and datacenter application – or for whoever will acquire the company, Nvidia being on top of the list.

Now, let’s have a look at the various IP vendors who have been successful, as well as IP categories growing share of the IP market.

Synopsys and Cadence, respectively #2 and #3, are growing respectively by 23.4% and 19%. This trend confirms the validity of one-stop-shop model, at least for large company benefiting from a wide sales organization. If you want to understand why Synopsys had better sales growth than Cadence, the answer is first linked with the wired interface IP category. Synopsys had 55% market share (Cadence 12.2%) in this category which grown by 22.4%, and IP sales have grown by an impressive 28% when for Cadence it was 20%. But Synopsys has been successful in many other categories, namely Analog & mixed-signal, Library & I/O, memory compiler or Others memory compiler. That’s why in 2020, Synopsys has confirmed his leader position for IP license sales with 30% market share, before ARM with 25.5%, and was strong #2 in IP sales with 19.2%.

We will see that the other winners in the IP market are, at the opposite, companies being extremely focused and able to be technical leaders on their segment or sub-segment. Let’s mention a few examples.

  • Alphawave, created in 2017 by a serial entrepreneur, Tony Pialis, enjoyed $25 million sales in 2019, based on advanced SerDes. In 2020, Alphawave sales has been multiplied by X3 to reach $75 million! We think that this incredible success is linked with their support of the most advanced interface IP protocols, PCI Express, 112G SerDes for Ethernet or D2D. These which are extensively used in hyperscalar, datacenter, networking or AI accelerators.
  • Silicon Creations, leader of the Analog Mixed-Signal (AMS) category in 2019 and 2018, and again in 2020, the company being about ten years old is now #1, just before Synopsys, with almost 35% growth.
  • Arteris IP with the Network-on-Chip (NoC), joining the Top 15 in 2019 is now #12 after the acquisition of Magillem with revenues above $40 million in 2020
  • Moortec was a good example, being focused on on-chip monitoring IP for IC on advanced technology node. So good that Moortec has been acquired in 2020 by Synopsys!

The next picture shows the weight of the various IP category in 2020. The main trend shown last year, the relative importance of wired interface growing more than all the other categories, is confirmed. Which is new is that the CPU category has stopped decreasing in 2020, like it did in 2019, 2018 and 2017.

Another interesting point to highlight is the percentage of IP business compared to the semiconductor business (less the memory business, DRAM and Flash). When the semiconductor (less memory) grew from $302B to $322B, or 6.8%, IP grew by 16.7%, almost 10% more than the semiconductor market.

We will see that this trend has been constant during the last 10 years (except in 2017 and 2018):

Eric Esteve from IPnest

To buy this report, or just discuss about IP, contact Eric Esteve (eric.esteve@ip-nest.com)

Also Read:

How SerDes Became Key IP for Semiconductor Systems

Interface IP Category to Overtake CPU IP by 2025?

Design IP Revenue Grew 5.2% in 2019, Good News in Declining Semi Market

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How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs

How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs
by gruggles on 04-12-2021 at 2:00 pm
Categories: IP, Synopsys

How PCI Express 6.0 Can Enhance Bandwidth Hungry High Performance Computing SoCs

What do genome sequencing, engineering modeling and simulation, and big data analytics have in common? They’re all bandwidth-hungry applications with complex data workloads. High-performance computing (HPC) systems deliver the parallel processing capabilities to generate detailed and valuable insights from these applications. To break through any bandwidth limitations, HPC SoCs need the fast data transfer and low latency that high-speed interfaces like PCI Express® (PCIe®) provide. With each new generation of PCIe delivering double the bandwidth of its predecessor, the latest iteration, PCIe 6.0, promises to be a boon for compute-intensive applications.

The HPC solutions that transform high volumes of data into valuable knowledge can be deployed in the cloud or on on-site data centers. Regardless, they demand compute, networking, and storage technologies with high performance and low latency, as well as artificial intelligence (AI) prowess. PCIe 6.0, which is expected to be released sometime this year, is expected to help solve the bandwidth limitations that HPC SoCs are constantly facing. The I/O bus specification will provide:

  • An increased data transfer rate of 64 GT/s per pin, compared to 32 GT/s per pin for PCIe 5.0
  • Power efficiency via a new low-power state
  • Cost-effective performance
  • Backwards compatibility to previous generations

Faster data transfer via PCIe 6.0 will result in faster computations for HPC, as well as cloud computing and AI applications. For example, as an AI algorithm is being trained, data needs to move back and forth quickly across multiple processors. PCIe 6.0 will remove the bottlenecks to allow a fast data flow for a more rapid training process. At the moment, the HPC landscape is dominated by hyperscale data centers. Given their disaggregated computing structure, hyperscale data centers currently provide the most powerful HPC capabilities for applications like AI engines. PCIe 6.0 will be beneficial by supporting more efficient disaggregated computing.

Another emerging application for PCIe 6.0 is storage, namely solid-state drives (SSD) used in data centers. Technology advances in SSD manufacturing—including stacked die—have increased storage capacity. At the same time, this has pushed the limits of 4-lane PCIe form factors. PCIe 6.0 will open the doors to the bandwidth and fast data transfer needed to take full advantage of the increased storage capacity.

New Architecture Brings New Challenges

PCIe 6.0 does come with a new architecture, moving from the non-return-to-zero (NRZ) structure with two logic levels of previous generations to Pulse Amplitude Modulation with four levels (PAM-4). PAM-4 encoding brings the increased data transfer rate and bandwidth. The latest generation also introduces forward error correction (FEC) to address raw bit error rate (BER) challenges that result from the new architecture. FEC traditionally introduces latency; however, PCI-SIG has defined a “lightweight FEC” with retry buffers and cyclic redundancy check (CRC) to maintain low latency. Another change in this iteration is the move to FLIT (flow control unit) mode, which also supports low latency and high efficiency.

PCIe 6.0 moves from the NRZ structure to PAM-4 for faster data transfer and higher bandwidth

Transitioning to this new architecture from earlier PCIe generations will involve some design considerations. For example, the receiver architecture for the PAM-4 PHY is based on an analog-to-digital converter, which calls for optimization of analog and digital equalization to achieve the optimal power efficiency regardless of the channel. Given the massive data pipe involved—potentially up to 1TB per second of data being moved in each direction—proper management of this data is critical. Another consideration relates to testbench development for verification, which ideally should be as efficient a process as possible while also accounting for factors like functional coverage.

Complete IP Solution for PCIe 6.0

Synopsys, which has long been a key contributor to PCI-SIG workgroups, has unveiled a complete IP solution that will allow for early development of PCIe 6.0 SoC designs. Synopsys DesignWare® IP for PCIe 6.0 is built on the silicon-proven DesignWare IP for PCIe 5.0 and supports the latest features of the upcoming new specification. As such, the solution is designed to address the bandwidth, latency, and power-efficiency demands of HPC, AI, and storage SoCs. The solution consists of:

  • The DesignWare Controller for PCIe 6.0, which utilizes a MultiStream architecture consisting of multiple interfaces to provide the lowest latency with maximum throughput for all data transfer sizes. Available in a 1024-bit architecture, the controller allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz.
  • The DesignWare PHY for PCIe 6.0, which provides unique, adaptive digital signal processing (DSP) algorithms that optimize analog and digital equalization for maximum power efficiency across backplane, network interface cards, and chip-to-chip channels. With its diagnostic features, the PHY enables near-zero link downtime. Its placement-aware architecture minimizes package crosstalk and allows dense SoC integration for x16 links.
  • Verification IP, which uses a native SystemVerilog/UVM architecture that can be integrated, configured, and customized with minimal effort to help accelerate testbench development while providing a built-in verification plan, sequences, and functional coverage.

Data Makes the World Go ’Round

It’s a data-driven world, and this will only intensify in the coming years. By 2025, according to IDC estimates, worldwide data will grow to 175 zettabytes, with as much of this data residing in the cloud as in data centers. That’s a 61% compounded annual growth rate from 33 zettabytes in 2018. While PCIe 6.0 early adopters are anticipated to be hyperscalers and other HPC SoC designers, the newest standard promises to eventually gain traction among designers working on edge, mobile, and automotive applications. While leading the shift to PCIe 5.0 with hundreds of design wins, Synopsys is helping designers gain a head-start on PCIe 6.0 designs with a complete PCIe 6.0 IP solution and expertise in the popular high-speed SerDes IP. As bandwidth demands increase, designers of PCIe 6.0-based applications can be well-positioned to keep the data moving.

By Priyank Shukla, Staff Product Marketing Manager, High-Speed SerDes IP, and Gary Ruggles, Sr. Staff Product Marketing Manager; Solutions Group
Also Read:

Why In-Memory Computing Will Disrupt Your AI SoC Development

Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud

USB 3.2 Helps Deliver on Type-C Connector Performance Potential

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eFPGA IP – in Videos

eFPGA IP – in Videos
by Daniel Nenni on 04-12-2021 at 10:00 am
Categories: eFPGA, Menta
2 Comments

Menta eFPGA IP

eFPGA has been a hot topic on SemiWiki for the past five years and it is still going strong. eFPGA is more descriptively categorized as embedded programmable logic and reconfigurable computing. Whatever you want to call it, eFPGA is an important piece of the computing puzzle, absolutely.

We recently did a series of videos with Menta that is worth seeing as a retrospective of were eFPGA is used today and some hints for tomorrow.

The first one is titled Design Adaptive eFPGA IP:

“In this webinar, we will explain what makes an eFPGA different to a FPGA but also to embedded CPUs/GPUs – and in which cases an eFPGA IP is the way to go. We will then explain what is a design adaptive eFPGA IP and why this adaptiveness is so important when it comes to integrating an eFPGA IP.”

The second one is titled: eFPGA Using Adaptive DSP:

“In this webinar, we will explain why the use of Menta Adaptive Digital Processor (DSP) makes Menta eFPGA different to any other FPGA, embedded CPUs/GPUs or eFPGA. We will then explain why its ease of use, its adaptiveness and its performance are so important when we are looking for the best trade-off between flexibility and PPA to better suit your hardware requirements”

The third one is titled: How to build a secure system over the time using eFPGA IP

“In this webinar we will present the Secure-IC & Menta corporate overview and vision, why eFPGA can be powerful in security, the first results of the collaboration, the joint value proposal summary, and what is coming next for eFPGA IP in secure Element.”

What is the value proposition of eFPGA you ask?

Secret protection: With Menta eFPGA you can wait to deliver your most proprietary technology to end-customers as a field-upgrade, minimizing any opportunity for competitors to reverse engineer your product.

Cost reduction: At higher production volumes, onboard FPGAs quickly become cost prohibitive. With Menta eFPGA you integrate on-board FPGA functionality.

Performance: With Menta eFPGA, sacrifices in board-space, I/O latency, and bandwidth disappear, as you bring those accelerators on-chip, without the limitations/overhead due I/O padcount or chip-to-chip communication interfaces.

Lower power: In a COT FPGA, all the extra to the programmable logic, such as high-speed interfaces, PLL, and controllers consume around half of the power. All our power saving advances lead an algorithm on a Menta eFPGA IP to consume between 10 and 50% of the power of the same algorithm on a FPGA.

Design insurance: Maximizing flexibility requires maximizing process-portability. Menta eFPGA is the only 100% standard-cell based solution and this approach enables rapidly porting your eFPGA to whatever new process geometry/variant you desire, using the same automated, standard EDA flow as for the rest of your SoC. Menta, using our industry gold-standard Synopsys-based implementation flow, enables portability within just weeks.

Security: In today’s global, multi-player design-chain, preserving IP/trade secrets is more critical and challenging than ever. With Menta eFPGA you can wait to deliver your most proprietary technology to end-customers as a field-upgrade, minimizing any opportunity for competitors to reverse engineer your product.

ABOUT MENTA
Menta is a privately held company based in Sophia-Antipolis, France. For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is the proven eFPGA pioneer whose design-adaptive standard cells-based architecture and state-of-the-art tool set provides the highest degree of design customization, best-in-class testability and fastest time-to-volume for SoC design targeting any production node at any foundry. For more information, visit the company website: www.menta-efpga.com