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Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!

Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
by Eric Esteve on 04-21-2023 at 6:00 am
Categories: IP, IPnest, Semiconductor Services

Top5 Royalty 2022 BIG updated

Design IP revenues had achieved $6.67B in 2022, after $5.56B in 2021, or 20.2% growth after 19.4% in 2021 and 16.7% in 2020. IPnest has released the “Design IP Report” in April 2023, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless Interface, Infrastructure and Misc. Digital) and by nature (License and Royalty).

The main trends shaking the Design IP in 2022 are very positive for most of the IP vendors, especially for 4 of the Top 5: ARM, Synopsys, Imagination and Alphawave growing by more than the market, respectively 24.5%, 22.1%, 23.1% and 94.7%. Rambus and Alphawave benefit from their recent IP vendor acquisition, PLDA, AnalogX and Hardent for the first, OpenFive for Alphawave, but their organic growth was already great. In summary, the Top 10 IP vendors have grown by 24.6%, when all others by 5.3%, this can be seen as an effect of consolidation, as a Top vendor will make proportionally more design win than “others”.

Synopsys, Alphawave and Rambus growth confirm again in 2022 the importance of the wired interface IP category (with 26.8% growth) aligned with the data-centric application, hyperscalar, datacenter, networking or AI. But the good performance of ARM and IMG proves the come back of the smartphone industry and the emergence of automotive as new growth vector for Design IP.

Looking at the 2016-2022 IP market evolution can bring interesting information about the main trends. Global IP market has grown by 94.8% when Top 3 vendors have seen unequal growth. The #1 ARM grew by 66.5% when the #2 Synopsys grew by 194% and Cadence (#3) by 203%. Market share information is even more significant. ARM move from 48.1% in 2016 to 41% in 2022 when Synopsys enjoy a move from 13.1% to 22% and Cadence is passing from 3.4% to 5.4%.

This can be synthetized with the comparison of 2016 to 2022 CAGR:

  • ARM CAGR 8.9%
  • Synopsys CAGR 19.7%
  • Cadence CAGR 20.3%

When the global IP market has seen 2016 to 2022 CAGR of 11.8%.

The strong information is that the Design IP market has enjoyed 11.8% CAGR for 2016-2022! Zooming on the categories (Processor, wired Interface, Physical, Digital), market share 2017 to 2022 evolution clearly shows interface category growth (18% to 24.9%) at the expense of processor (CPU, DSP, GPU) declining from 57.6% to 49.5%. When Physical and Digital are almost stable, as it can be seen on the above picture.

Being very synthetic, Design IP markey is split in quarter:

  • Processor (CPU, DSP, GPU) weigth one half (two quarter)
  • Wired Interface weight one quarter
  • Digital and Physical one quarter in total

IPnest has also calculated IP vendors ranking by License and royalty IP revenues:

Synopsys is the clear #1 by IP license revenues with 29.7% market share in 2022, when ARM is #2 with 25.2%. Alphawave, created in 2017, is now ranked #4 just behind Cadence, showing how high performance SerDes IP is essential for modern data-centric application (Alphawave is leader for PAM4 112G SerDes available in 7nm, 5nm and 3nm from various foundries, TSMC, Samsung and Intel-IFS). Analyze written last year stay valid!

The 2022 ranking for Royalty shows ARM’s dominance with 63.8% market share, not a surprise if we consider their customer installed base and their strong position in the smartphone industry. Imagination Technologies (IMG) position of #3 is consistent. Interesting to notice, both companies are expected to IPO in 2023…

With 20% YoY growth in 2021 and 2022, the Design IP industry is simply confirming how incredibly healthy is this niche within the semiconductor market and the past 2016 to 2022 CAGR of 11.8% is a good metric!

IPnest has also run a 5-year forecast (not yet published) for Design IP, to pass $10B in 2025 and predict a future CAGR (2021 to 2026) of 16.7%. Optimistic? This year-to-year 2022 growth is on-line with this prediction…

Eric Esteve from IPnest

To buy this report, or just discuss about IP, contact Eric Esteve (eric.esteve@ip-nest.com)

Also Read:

Interface IP in 2021: $1.3B, 22% growth and $3B in 2026

Stop-For-Top IP Model to Replace One-Stop-Shop by 2025

Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%

Chiplet: Are You Ready For Next Semiconductor Revolution?

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S2C Helps Client to Achieve High-Performance Secure GPU Chip Verification

S2C Helps Client to Achieve High-Performance Secure GPU Chip Verification
by Daniel Nenni on 04-20-2023 at 6:00 am
Categories: EDA, Prototyping, S2C EDA
1 Comment

S2C Prototyping 2023

S2C, a leading provider of FPGA-based prototyping solutions, has helped a client achieve high-performance secure GPU chip verification. With the help of S2C’s Prodigy prototyping solution, the client was able to start software development and hardware-software co-design early, leading to accelerated time-to-market for their entire chip product and enabling them to seize early opportunities in the market.

A Graphics Processing Unit, or GPU chip for short, is a specialized processor designed to handle image and video data. Its primary purpose is to perform many parallel computations to process massive data more efficiently. Due to this characteristic, GPUs are highly suitable for graphics rendering, video encoding, and decoding tasks. In recent years, GPUs have also found widespread use in areas like deep learning, scientific computing, and cryptography because of their significant speed improvements in computation.

One of the major challenges for GPU vendors is the intense competition in this field. S2C’s customers was a new entrant to the GPU market, and they tackled this challenge by applying a shift-left strategy to accelerate the GPU chip’s time-to-market and seizing the market’s early opportunities. The client’s design cycle spanned 18 months from concept design, development, and verification, tape-out delivery to chip sample illumination, which included their own GPU core IP, processor architecture optimization, compilers, verification models, software drivers, and system compatibility. The entire process was completed in one go.

S2C prototyping solution included a diverse selection of daughter cards such as PCIe, HDMI, DDR, and GPIO that made it incredibly convenient to build a GPU verification system. Our client opted for S2C’s Prodigy Virtex UltraScale VU440 Logic Systems, which consisted of one Quad platform and one Dual platform, and achieved an impressive FPGA utilization rate of 71%.

As the client stated, “S2C’s Prodigy prototyping solution enabled us to achieve high-performance secure GPU chip verification, which helped us to gain an advantage in the competitive GPU market. With S2C’s support, we were able to accelerate our time-to-market, which was  critical to our success.”

For the new IC design verification, the IC verification team plans to use Prodigy S7-19P, which is based on the Xilinx Virtex UltraScale+ VU19P FPGA. The S7-19P prototyping platform provides 1.6 times more logic and delivers a 30% performance boost compared to its predecessor, making it an excellent choice for hype-scale design verification.

S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 6 of the world’s top 15 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea and Japan.

Also Read:

Ask Not How FPGA Prototyping Differs From Emulation – Ask How FPGA Prototyping and Emulation Can Benefit You

A faster prototyping device-under-test connection

Stand-Out Veteran Provider of FPGA Prototyping Solutions at #59DAC

Multi-FPGA Prototyping Software – Never Enough of a Good Thing

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What’s New with Cadence Virtuoso?

What’s New with Cadence Virtuoso?
by Daniel Payne on 04-19-2023 at 10:00 am
Categories: Cadence, EDA

Virtuoso Place and Route min

It was back in 1991 that Cadence first announced the Virtuoso product name, and here we are 32 years later and the product is alive and doing quite well. Steven Lewis from Cadence gave me an update on something new that they call Virtuoso Studio, and it’s all about custom IC design for the real world. In those 32 years we’ve seen the semiconductor process march along Moore’s Law from 600nm using planar CMOS, scaling down to the FinFET era below 22 nm, reaching GAA at the 3nm node. Clearly the EDA tool demands have changed as smaller nodes brought on new physical effects that needed to be modeled and simulated to ensure first silicon success.

The focus of Cadence Virtuoso Studio is to help IC designers take on the present day challenges through six areas:

  • Increased process complexity
  • Handling 10,000s of circuit simulations
  • Design automation and circuit migration
  • Heterogenous integration
  • AI
  • Sign-off, in-design verification and analysis

The Virtuoso ADE (Analog Design Environment) allows circuit engineers to explore their analog, mixed-signal and RFIC designs through schematic capture and circuit simulation. The architecture of Virtuoso ADE has been revamped for better job control, reducing RAM usage, and speeding up simulations by using the cloud. For one example the RAM required to run Spectre on 10,000s of simulations was reduced from 420MB down to just 18MB for simulation monitoring, while expression evaluations decreased from 420MB of RAM to just 280MB.

Updates to the Virtuoso Layout Suite include four choices of place and route technology, each suited to the unique task at hand through the Virtuoso environment:

Four P&R Technologies

DRC and LVS runs are part of physical verification, and running these in batch mode, fixing and repeating, leads to long development schedules. In-design verification allows the interactive use of DRC and LVS while working on an IC layout, so feedback on what to change is quickly highlighted, accelerating productivity. A layout designer using Virtuoso Layout Suite benefits from in-design verification using the Pegasus DRC and LVS technology.

Chiplets, 2.5D and 3D packaging span the traditionally separate realms of PCB, package and IC design domains. Virtuoso Studio enables the co-design and verification of packages, modules and ICs by:

Looking into the near future you can expect to see details emerge about how AI is being applied to automatically go from an analog schematic into layout  based on machine learning and specifications. These auto-generated trial layouts will further speed up a very labor intensive process. A second development area for AI to be applied is the problem of migrating custom analog IP to a new process node. Stay tuned.

Analog IP migration

Early customers of Virtuoso Studio include Analog Devices for the co-design of IC and package, leading-edge IC consumer designs at MediaTek, and AI-based process migration at Renesas.

Summary

Virtuoso Studio has put into release 23.1 some impressive new features that IC design teams can start using to be more productive. The Virtuoso infrastructure has changed to meet the challenges of Moore’s Law, simulations with 10,000s circuit simulations are practical, RFIC and module 2.5D/3D co-design are supported, in-design DRC/LVS verification takes much less time, and AI is being applied to automate analog tasks.

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Electronics Production in Decline

Electronics Production in Decline
by Bill Jewell on 04-19-2023 at 6:00 am
Categories: Semiconductor Intelligence, Semiconductor Services
2 Comments

Unit Change Electronics 2023

Shipments of PCs and smartphones were weak in 2022 and continue to decline in 2023. For the first quarter of 2023, IDC estimated PC shipments dropped 29% from a year earlier. This follows a 28% year-to-year decline in 4Q 2022. For the year 2022, PC shipments declined 16% from 2021, the largest year-to-year decline in the history of PCs. The outlook for the rest of 2023 is not encouraging, with Gartner forecasting a 12% decline in year 2023 PC shipments. The PC market collapsed after the end of the boom during the COVID-19 pandemic. Global economic uncertainty is contributing to the current PC market weakness.

IDC estimated smartphone shipments in 4Q 2022 dropped 18% from a year earlier, resulting in an 11% decline in year 2022 shipments, the largest decline ever. Smartphones rebounded from a 7% decline in 2020 (driven by pandemic-related production slowdowns) to 6% growth in 2021. As with PCs, the current economic uncertainty is impacting smartphone shipments. DigiTimes estimates 1Q 2023 smartphone shipments dropped 13% from a year ago. IDC projects a 1% decline in smartphone shipments for the year 2023.

The weakness in PCs and smartphones is reflected in production data from China. Although some electronics manufacturing has shifted out of China in the last few years, China still accounts for about two-thirds of smartphone production (according to Counterpoint Research) and the vast majority of PC production. China’s three-month-average change versus a year ago (3/12) for PCs turned negative in April 2022 and the decline has been greater than 20% for the last three months ending in February 2023. Mobile phone production change (primarily smartphones) was negative for seven of the last nine months, with the decline in the last two months greater than 10%. Total China electronics production measured in local currency (yuan) showed 3/12 change turning negative in January 2023, the first decline since the early months of the pandemic in 2020.

Countries which have benefited from electronics production moving out of China are also showing a slowdown. Malaysia and Taiwan both reported strong electronics production growth in most of 2022, with 3/12 change mostly above 20% and approaching 30% in several months. In the latest data, 3/12 change dropped below 10% in January for Taiwan and in February for Malaysia. Vietnam 3/12 change was over 20% in 2Q 2022 but has been decelerating each month since June 2022. Vietnam’s 3/12 change turned negative at minus 1% in February 2023, the same as China. In March 2023, Vietnam was at minus 5%.

The more mature electronics manufacturing regions have not been as affected by the slowdown in PCs and smartphones. The United States, Japan, United Kingdom and the 27 countries of the European Union (EU 27) are less dependent on consumer electronics. Electronics production in these countries is largely industrial, automotive, communications infrastructure and enterprise computing. However, many of these countries are experiencing moderating growth. The EU 27 3/12 change in electronics production ranged primarily between 10% and 20% for most of 2022. In January 2023, the 3/12 changed dropped to 7%. The U.S. experienced a moderate acceleration in 3/12 growth through most of 2022, increasing from 3% in January 2022 to over 8% in the last three months of 2022. U.S. growth had been decelerating in 2023, dropping below 6% in February. In contrast, Japan and the UK electronics production was in decline for much of 2022. Japan 3/12 turned positive in October 2022 and was 4% in February 2023. The UK 3/12 turned positive in October 2022 at 0.9%. After a 0.7% decline in January 2023, the UK 3/12 bounced back to 0.8% in February 2023.

As stated in our February 2023 Semiconductor Intelligence newsletter, the outlook for semiconductors in 2023 is bleak. In addition to weak end demand in many electronics markets, many semiconductor companies are dealing with excess inventory and pricing pressures. Despite a few bright spots such as automotive (March 2023 newsletter), the overall semiconductor market will not recover until end demand of key end equipment such as PCs and smartphones reverses its decline.

Also Read:

Automotive Lone Bright Spot

Bleak Year for Semiconductors

CES is Back, but is the Market?

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Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links

Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
by Kalar Rajendiran on 04-18-2023 at 10:00 am
Categories: EDA, Siemens EDA

Pre and Post FEC BER as FEC Matrix size Reduces

As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and distortion. The DFE scheme relies on decisions about the levels of previous symbols (high/low) to correct the current symbol. This allows the DFE to account for distortion in the current symbol that is caused by the previous symbols.

However, DFE error propagation can occur when feedback signals are incorrect. Following are some of the situations that contribute to DFE error propagation. DFE circuits operate by using feedback to equalize the received signal, but this feedback can also amplify noise and distortion in the signal. In some cases, the feedback can overemphasize certain frequencies, leading to an increase in noise at those frequencies and an increase in the Bit Error Rate (BER). The mechanism also relies on accurate timing to make decisions about the incoming data. If there are timing errors in the feedback loop, these errors can propagate and cause additional errors in the received data. Nonlinear distortion in the transmission channel can also cause DFE circuits to make incorrect decisions about the received data. These errors can then propagate through the feedback loop and cause additional errors in the data. As the DFE scheme makes decisions based on previous decisions, errors in the feedback loop accumulate over time.

As noted above, DFE error propagation can lead to increased BER and reduced signal integrity. Increased BER in turn leads to data errors and reduced system performance. Reduced signal integrity results in increased jitter and reduced eye height, leading to errors in data transmission. As a result, DFE error propagation can significantly impact the performance of high-speed SerDes circuits and must be carefully managed to ensure reliable data transmission.

But existing statistical simulation methods cannot properly consider DFE feedback, and time-domain simulations become impractical for low error probabilities. A whitepaper by Siemens EDA presents a statistical solver that can find bit error ratio or symbol error ratio in the presence of isolated and burst DFE errors. The solver can accurately consider transmit and receive jitter, crosstalk aggressors, noise, and other impairments, and is useful in choosing forward error correction (FEC) schemes and parameters. The paper defines the essential building blocks of the statistical solver, including the main elements of statistical analysis, the convolution term for DFE feedback, the symbol error probability matrix, and the flow to find BER/SER metrics. It also discusses the use of a modified iteration process to find the probability distribution of symbol error groups and presents experimental results of the statistical solver.

The following are some excerpts from the whitepaper.

Building statistical eye that includes DFE errors

The method is considered a Markov chain with a transition operator defined by a function that transforms known error probabilities into new error matrices measured from the eye diagram. The process involves building a statistical eye diagram from which error probabilities are calculated. The iterations continue until the error probability matrices become equal up to machine precision. The iterations are consistent and converge to the same solution regardless of initial settings. Two examples are given to illustrate the convergence of the iterations with statistical solver in the loop. The first example is the simulation of a 200GBASE-CR4 link, while the second is the CEI VSR channel with 4 taps DFE.

Choosing FEC parameters

The size of FEC needed to correct the error groups can be determined by analyzing the probability parameters distribution of error groups found from statistical simulation.

The simulations with FEC demonstrate the importance of knowing the burst error distributions for the proper choice of FEC parameters while keeping the FEC-induced latency to a minimum. The statistical analysis results can be relied upon for the purpose of FEC parameter optimization for a large variety of channels.

Summary

The whitepaper presents a novel statistical simulation method that considers the effect of DFE error propagation in SerDes links. Simulation speeds are sufficient to make this approach a routine part of the design process that require multiple channel compliance evaluations and FEC parameter optimization. You can download the entire whitepaper from here.

Also Read:

Hardware Root of Trust for Automotive Safety

Siemens EDA on Managing Verification Complexity

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Can Attenuated Phase-Shift Masks Work For EUV?

Can Attenuated Phase-Shift Masks Work For EUV?
by Fred Chen on 04-18-2023 at 6:00 am
Categories: Lithography

1679926948898

Normalized image log-slope (NILS) is probably the single most essential metric for describing lithographic image quality. It is defined as the slope of the log of intensity, multiplied by the linewidth [1], NILS = d(log I)/dx * w = w/I dI/dx.  Essentially, it gives the % change in width for a given % change in dose. This is particularly critical for EUV lithography, where stochastic variations in dose are naturally occurring.

A dark feature against a bright background has a higher NILS than a bright feature against a dark background. The reason is the intensity in the denominator is relatively much lower for the dark feature than the bright feature. For this case, the NILS is also made sufficiently high, e.g., > 2, with a sufficiently high mask bias, i.e., a dark feature size on the mask larger than 4x the targeted wafer dark feature size. However, if the dark feature on the mask is too large compared to the spacing between features, then there is too little light reaching the wafer. This means that a longer exposure time is needed to accumulate a sufficient number of photons absorbed. A way around this is to use an attenuated phase shift mask, or attPSM in abbreviation. The dark feature is actually partially transmitting light through the mask, and imparting a phase shift of 180 degrees. Both transmission (or reflectivity in the case of EUV) and phase are adjusted by the material and thickness of the dark feature on the mask.

Figure 1. The same NILS requires much longer exposure with a binary (T=0) mask than a 6% attPSM. This is based on a 4-beam image of dark island feature (width w, pitch p) in an expected quadrupole illumination scenario.

In Figure 1, we see that with the same NILS, the log-slope curves are similar in shape, but the attPSM with less bias than the binary mask allows more light to get to the wafer, so that a long exposure is not needed.

With the advantage of using an attPSM made clear, let’s turn now to why EUV hasn’t implemented any yet. A fundamental difference between an EUV mask and a DUV mask is that while there is only single pass of light through the DUV mask, the EUV mask has two passes of light through the pattern layer, and in between passes, the light propagates through a multilayer, which tends to absorb more light at higher angles [2].

Figure 2. While a DUV mask (left) is treated as a thin pattern layer, an EUV mask (right) is treated as two pattern layers separated by an absorbing layer, i.e., the multilayer.

Consequently, the phase shift (also no longer targeted at 180 degrees, but over 200 degrees [2]) is distributed over multiple layers, and not easily tailored by adjusting one layer’s thickness. Moreover, the known candidate materials are hard to process with good control. Materials like ruthenium and molybdenum easily oxidize. A few nanometers change of thickness can add tens of degrees of phase shift [3]. The different individual wavelengths within the 13.2-13.8 nm range also have significantly different phase shifts as well as reflectivities from the multilayer [4]. Regardless of these complicating factors, designing attPSMs for EUV continues to be a topic of ongoing investigation [5].

References

[1] C. A. Mack, “Using the Normalized Image Log-Slope,” The Lithography Expert, Microlithography World, Winter 2001: http://lithoguru.com/scientist/litho_tutor/TUTOR32%20(Winter%2001).pdf

[2] C. van Lare, F. Timmermans, J. Finders, “Mask-absorber optimization: the next phase,” J. Micro/Nanolith. MEMS MOEMS 19, 024401 (2020).

[3] I. Lee et al., “Thin Half-tone Phase Shift Mask Stack for Extreme Ultraviolet Lithography,” https://www.euvlitho.com/2011/P19.pdf

[4] A. Erdmann et al., “Simulation of polychromatic effects in high NA EUV lithography,” Proc. SPIE 11854,1185405 (2021).

[5] A. Erdmann, H. Mesilhy, P. Evanschitzky, “Attenuated phase shift masks: a wild card resolution enhancement for extreme ultraviolet lithography?,” J. Micro/Nanopattern. Mater. Metrol. 21, 020901 (2022).

This article first appeared in LinkedIn Pulse as Phase-Shifting Masks for NILS Improvement – A Handicap For EUV?

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Lithography Resolution Limits: The Point Spread Function

Sino Semicap Sanction Screws Snugged- SVB- Aftermath more important than event

Resolution vs. Die Size Tradeoff Due to EUV Pupil Rotation

KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too

Podcast EP155: How User Experience design accelerates time-to-market and drives design wins

Podcast EP155: How User Experience design accelerates time-to-market and drives design wins
by Daniel Nenni on 04-17-2023 at 10:00 am

Dan is joined by Matt Genovese. Matt founded Planorama Design, a user experience design professional services company to design complex, technical software and systems that are simple and intuitive to use while reducing internal development and support costs. Staffed with seasoned engineers and user experience designers, the company is headquartered in Austin, Texas.

Matt explains how Planorama Design helps hardware companies create simple, intuitive user experiences for the software they ship with their products. Matt explains the process used and the substantial business benefits their customers are seeing.

You can also learn more at the LIVE WEBINAR Matt will conduct on April 25 at 9AM Pacific time, entitled The ROI of User Experience Design: Increase Sales and Minimize Costs. You can register for the webinar HERE.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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AI Assists PCB Designers

AI Assists PCB Designers
by Daniel Payne on 04-17-2023 at 6:00 am
Categories: AI, Cadence, EDA

PCB steps min

Generative AI is all the rage with systems like ChatGPT, Google Bard and DALL-E being introduced with great fanfare in the past year. The EDA industry has also been keen to adopt the trends of using AI techniques to assist IC engineers across many disciplines. Saugat Sen, Product Marketing at Cadence did a video call with me to explain what they’ve just announced, it’s called Allegro X AI. The history of Cadence includes both IC and Systems-design EDA tools, plus verification IP and design services.

By using generative AI-driven PCB design in Allegro X AI there are three big goals:

  • Better and Faster Hardware Design
  • Improved PCB Designer Productivity
  • PCB-design Driven by Physics engines

The typical PCB design flow has several sequential steps, where the most time-consuming parts are manual placement, followed by manual routing.

PCB Steps

With Allegro X AI the electrical engineer specifies design constraints, runs the tool; automating board placement, power and ground routing, plus critical signal routing.

Allegro X AI tool flow

Just like ADAS in the automotive world is bringing new automation levels to the driving experience, constraint-driven PCB design offers a shift-left time savings for electronic systems. Allegro X AI does not replace PCB designers, rather it makes the team of electrical engineer plus PCB designer more productive, saving valuable time to market.

To provide these new automation levels to the PCB design flow requires compute power found in the cloud, and one example of a PCB design that required 3 days for human-based placement, now takes only 75 minutes with Allegro X AI while producing a 14% better wire length metric.

Global Placement comparison

A second PCB example that Saugat showed me was for global placement and the automation results were impressive:

  • 20 minute runtime with Allegro X AI versus 3 human days
  • 0 opens, 0 DRCs, with 100% timing passes
  • Wire length improved by 3% using AI

In this new, AI-powered approach, the PCB designer still needs to complete detailed routing, but stay tuned for future improvements. With Allegro X AI an electrical engineer can quickly look at the feasibility of a PCB design, without using a layout designer resource. The learning curve for this new feature is quick, so expect to explore results on the very first day of use. Expect to use this technology on small to medium-sized PCB projects to start out with. The built-in engines for SI/PI analysis operate quickly, ensuring that your design meets timing and reliability constraints.

In the official press release you can read quotes from three companies that had early access to Allegro X AI:

Summary

PCB design is changing, and for the better by using AI techniques found in tools like Allegro X AI from Cadence. You can expect benefits like better and faster hardware design, as an electrical engineer can explore the PCB design space more quickly, even giving the PCB designer a layout starting point. PCB designers become more productive, as the placement and critical net routing becomes automated, freeing them up to complete the detailed routing task. Using constraints and built-in analytics for SI/PI is a physics-based approach, which helps produce a more optimal PCB design compared to fully manual Methods.

Cadence engineered all of this AI technology in-house, and you just need to contact your local account manager to get started with Allegro X AI.

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Podcast EP154: The Future of Custom Silicon – Views From Alphawave Semi’s Sudhir Mallya

Podcast EP154: The Future of Custom Silicon – Views From Alphawave Semi’s Sudhir Mallya
by Daniel Nenni on 04-14-2023 at 10:00 am

Dan is joined by Sudhir Mallya, Senior Vice President of Corporate Marketing at Alphawave Semi. He is based in Silicon Valley and has over 25 years of experience at leading global semiconductor companies with executive positions in engineering, marketing, and business unit management. His experience spans custom silicon and application-specific products across multiple domains including data centers, networking, storage, and edge-computing.

Dan explores the future of custom silicon with Sudhir. Key drivers, including data center, automotive and edge/IoT are discussed. The tradeoffs between custom and off-the-shelf design is also explored, along with the importance of interface standards and design challenges that lie ahead.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Multi-Die Systems: The Biggest Disruption in Computing for Years

Multi-Die Systems: The Biggest Disruption in Computing for Years
by Daniel Nenni on 04-14-2023 at 6:00 am
Categories: Chiplet, EDA, Events, Synopsys

SNUG Panel 1

At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. The discussion was based on a report published by the MIT Technology Review Insights in cooperation with Synopsys. This is a very comprehensive report (12 pages) that is available online HERE.

Here is the preface of the MIT paper:

“Multi-die systems define the future of semiconductors” is an MIT Technology Review Insights report sponsored by Synopsys. The report was produced through interviews with technologists, industry analysts, and experts worldwide, as well as a cross-industry poll of executives. Stephanie Walden was the writer for this report, Teresa Elsey was the editor, and Nicola Crepaldi was the publisher. The research is editorially independent, and the views expressed are those of MIT Technology Review Insights. This report draws on a poll of the MIT Technology Review Global Insights Panel, as well as a series of interviews with experts specializing in the semiconductor industry and chip design and manufacturing. Interviews occurred between December 2022 and February 2023.

The focus of a panel like this is the participants. During our lunch prior to the panel I learned quite a bit:

Simon Burke, AMD Senior Fellow, has 25+ years experience building chips starting with HPC vendor Silicon Graphics. He them moved to AMD then to Xilinx and back to AMD through the acquisition. An amazing journey, both depth of knowledge and a great sense of humor. Simon and AMD are leaders in the chiplet race so there was a lot to be learned here.

John Lee, Head of Electronics, Semiconductors and Optics at Ansys, is a serial entrepreneur. I met John when Avant! bought his Signal Integrity company in 1994. Synopsys then bought Avant! In 2002 and John became R&D Director. John then co founded Mojave Design which was acquired by Magma in 2004. John left Magma after they were acquired by Synopsys and later founded Gear Design, a big data platform for chip design, which was acquired by Ansys in 2015.  John is one of my favorite panelists, he says it like it is.

Javier DeLaCruz has 25+ years of experience including a long stint with one of my favorite companies eSilicon. Javier works for Arm handling advanced packaging technology development and architecture adaption including 2.xD and 3D systems. Arm is everywhere so this is a big job.

Francois Piednol is Chief Architect at Mercedes Benz but prior to that he spent 20 years at Intel so he knows stuff. Francios is also a member of UCIe and a jet pilot. He actually owns a jet and as a pilot myself I could not be more impressed. Francios was part of the MIT Chiplets paper mentioned above as well so he is a great resource.

Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys, he currently leads engineering for 3DIC, advanced technology and visualization. He has over 25 years of R&D experience in EDA where he has led development across the spectrum of digital implementation, including placement, routing, optimization, timing, signal integrity and electromigration. He has previously led efforts on EDA enablement and collaborations for emerging silicon technologies nodes. Henry knows EDA.

Dan Kochpatcharin is the Head of Design Infrastructure Management Division at TSMC. Dan is a 30+ year semiconductor professional with 25 years at foundries. For the past 15 years Dan has been instrumental in the creation of the TSMC OIP. Today he leads the OIP Ecosystem Partnerships: 3DFabric Alliance, IP Alliance, EDA Alliance, DCA, Cloud Alliance, and VCA. Dan K, as we call him, knows the foundry business inside and out. I always talk to Dan whenever I can.

Here is the abstract for the panel:

The new era of multi-die systems is an exciting inflection point in the semiconductor industry. From high-performance and hyper-disaggregated compute systems to fully autonomous cars and ultra-high-definition vision systems; multi-die chip designs will transform computing possibilities, driving many new innovations, expanding existing markets and paving the way for new ones. Critical to fueling this momentum is the coherent convergence of innovations across the semiconductor industry by EDA, IP, chiplet, foundry and OSAT leaders. But what’s really happening inside the companies driving what can have one of the biggest impacts on system design and performance in a very long time?

Join this panel of industry leaders who are at the forefront of shaping the multi-die system era. Many have already made the move or are making key contributions to help designers achieve multi-die system success. Listen to their insights, their views on how multi-die system approaches are evolving, and what they see as best practice. Hear about the near, medium, and long-term future for multi-die innovation.

Here are the questions I asked:

Why Multi-Die System and Why Now?
  1. Mercedes: What is driving the change, and what is multi-die system offering you?
  2. AMD: How do you see the trend to multi-die at AMD and what is the key driver?
  3. Synopsys: Are we seeing other markets move in this direction?
  4. TSMC: How are you seeing the overall market developing?
It Takes a Village?
  1. Arm: How are companies like Arm viewing the multi-die opportunity and how does something like multi-die impact the day-to-day work for designers and system architects working with Arm?
  2. Ansys: how is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
  3. Synopsys: What other industry collaborations, IP, and methodologies are required to address the system-level complexity challenge?
It’s Just the Beginning?
  1. TSMC: Which technologies are driving the multi-die growth trend and how do you see these technologies evolving over time?
  2. AMD: When do you foresee true 3D – logic-on-logic – entering the arena for AMD and what kind of uplift would if offer compared to infinity fabric style connectivity solutions.
  3. Synopsys: How are the EDA design flows and the associated IP evolving and where do customers want to see them go?
Designing Multi-Die Systems?
  1. Mercedes: How is the multi-die design challenge being handled at Mercedes and is it evolving in lock-step – true HW/SW co-design – with these ongoing software advancements?
  2. AMD: What methodology advancements would you like to see across the industry to make system development more efficient? And what kind of impact does multi-die sytem design have on block designers?
  3. Ansys: How is the increased learning curve for these multi-physics effects being addressed?
  4. Arm: How is the Arm core design flow evolving to absorb these new degrees of freedom?
  5. Synopsys: how is EDA ensuring that designers can achieve the entitlement promised in their move to multi-die?
  6. TSMC: How is TSMC working with EDA and OSAT partners to simplify the move to multi-die design?
The Long Term?
  1. Mercedes: How is Mercedes approaching the long-term reliability challenge?
  2. TSMC: How is TSMC dealing with process reliability and longevity for these expanding use cases?
  3. Ansys: What is the customer view of the reliability challenge?
  4. Synopsys: Do you see multi-die system as a significant driver for this technology moving forward?

(I can cover the answers to these questions in a second blog)

Summary

The answers to most of the questions are covered in the MIT paper but here are a couple of points that I rang true to me:

Chiplets are truly all about the ecosystem. So many companies could be involved, especially for chip designers that are using commercial chiplets, so where is the accountability? Dan K. made a great point about working with TSMC because they are the ecosystem experts and the buck stops with the wafer manufacturer. The TSMC ecosystem really is like the semiconductor version of Disneyland, the happiest place on earth.

Another point that was made, which was a good reminder for me, is that we are at the beginning of the chiplet era and the semiconductor industry is very fast moving. Either you harness the power of chiplets or the power of chiplets will harness you, my opinion.

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