Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform some narrow function in a single domain, and it’s up to the EDA user to control the tool, read the results, and then iterate while manually optimizing.
In the late 1980’s we saw the birth of smarter EDA tools like logic synthesis, which at first only optimized a gate level netlist into a reduced form, then later accepted RTL language and produced an optimized, process-specific, gate-level netlist. By the mid 2000’s there was an application of Machine Learning (ML) to Monte Carlo simulations for SPICE simulators, saving circuit designers time and effort. Recently, even Google has applied ML to produce better placement results for large SoC designs than what a human can produce. The trends have been clear, EDA tool developers have created smarter tools, but mostly limited to single domains, like: Logic design, SPICE and floor planning.
On June 7 some big news in EDA came from Cadence, as they announced something called Optimally Intelligent System Explorer, an AI-based approach for Multidisciplinary Design Analysis and Optimization (MDAO). The days of separated silos of EDA tools operating in only one domain are changing into more complex, multi-domain tools. Cadence has gone so far as to organize a Multi-Physics System Analysis Group, where Ben Gu is the Vice President. The new product name isOptimality Explorer, and it works across three system-level EDA tools:
- Clarity – 3D Electromagnetic (EM) field solver
- Sigrity X – Distributed simulation for signal and power integrity (SI/PI)
- Celsius – Thermal solver (Optimality integration coming soon)
The diagram above shows a system design where a communication channel consists of an IC driver, package, PCB layout, package, and finally a receiver inside the final IC. Criteria for success is optimizing the physical layouts to ensure an acceptable return and insertion loss, while managing cross-talk issues and maintaining signal isolation. Optimality Explorer is used to automatically guide optimization, using both the Clarity and Sigrity X tools, and it decides what to change for each tool run, and figure out when an optimal solution has been found.
For example, the system designer specifies that return loss has to be lower than some threshold, and then Optimality Explorer reads from Allegro, creates design variables, controls the optimization process, and finds the optimum solution. Here’s a plot from an optimization run where the criteria was a return loss under -35dB:
The blue dots each represent an iteration during optimization, and the red line is the progress towards reaching the design goal. This automated method for optimization happens much faster than the manual approaches used for the past decades. Cadence is claiming a 10X faster time to optimization by using Optimality.
The theory of applying ML to optimization sounds good, but what about real world results? Great question. At DesignCon there was a presentation by Kyle Chen of Microsoft, where they used Optimality to optimize micro-stacked vias in a rigid-flex PCB. Kyle wrote, “As an early adopter of the Cadence Optimality Intelligent System Explorer, we stressed its performance on a rigid-flex PCB with multiple via structures and transmission lines. The Optimality Explorer’s AI-driven optimization allowed us to uncover novel designs and methodologies that we would not have achieved otherwise. Optimality Explorer adds intelligence to the powerful Clarity 3D Solver, letting us meet our performance target with accelerated efficiency.”
This approach may sound familiar to Cadence IC designer users in the RTL to GDS flow, because last year they announced Cerebrus, an AI approach using ML to explore the design space for Power, Performance and Area (PPA) through placement, routing and timing closure. The same kind of reinforcement ML in Cerebrus has also been used in Optimality Explorer.
EDA tools have been used to create every AI chip every designed, and now AI and specifically ML is being applied to EDA tools like Optimality Explorer, to explore the design space of systems by optimizing more quickly than manual methods. The first two tools from Cadence that work with Optimality Explorer are Sigrity X and Clarity, then expect Celsius to be the next tool added. Multi-physics EDA, or multidisciplinary design analysis and optimization (MDAO) has begun in earnest.
- Cerebrus, the ML-based Intelligent Chip Explorer from Cadence
- #56DAC – Machine Learning and its impact on the Digital Design Engineer
- More Than Moore and Charting the Path Beyond 3nm
- Clarity 3D Transient Solver Speeds Up EMI/EMC Certification
- Solving the EM Solver Problem
- Bridging the Gap Between Design and Analysis