SemiWiki – Page 198 – The Open Forum for Semiconductor Professionals

October 18, 2022October 17, 2022

Balancing Analog Layout Parasitics in MOSFET Differential Pairs

Balancing Analog Layout Parasitics in MOSFET Differential Pairs
by Daniel Nenni on 10-18-2022 at 6:00 am
Categories: EDA, Pulsic

This article is an abstract of Paul Clewes’ webinar you can find here.

Differential amplifiers apply gain not to one input signal but to the difference between two input signals. This means that a differential amplifier naturally eliminates noise or interference that is present in both input signals. Differential amplification also suppresses common mode signals. In other words, a DC offset that is present in both input signals will be removed, and the gain will be applied only to the signal of interest. In most real-world applications, the differential pair is connected to a current mirror or an active load. This vastly decreases the amount of silicon area that is required and greatly increases the gain.

The differential pair in analog layout is all about balance. Therefore, for optimal performance, its MOSFETs must be matched. This means that the channel dimensions of both MOSFETs must be the same, and the routing should be balanced. Any difference in the parasitics of the left and right sides of the differential pair will reduce its performance.

We can easily demonstrate all these layout concepts using a traditional schematic editor and a plugin provided by Pulsic. Pulsic’s plugin is called Animate Preview and generates a DRC clean layout for an analog circuit that is loaded into a schematic editor. Animate runs in the background and automatically recognizes key structures like differential pairs and current mirrors. It also automatically constrains the placement to generate a human-quality placement, including differential pairs.

Animate creates multiple layouts for your circuit and shows the layout directly inside your traditional schematic editor.

Here is an image showing the Animate Preview plugin window. On the right-hand side of the window, we have numerous automatically generated layouts. All of these layouts are for this one schematic. At the bottom, we have the constraints. These constraints are all automatically generated by Animate. And on the left-hand side, we have some stats for each of the generated layouts.

Animate’s multiple initial layouts can be seen on the right-hand side.

Clicking a differential pair will highlight its position in the layouts.

We can see that Animate has automatically detected the differential pair for us, and it has drawn a halo around the two devices in the differential pair directly on the schematic. If we look at the constraints options, we can see that animate has recognized these two devices as being a differential pair, and it has automatically constrained the layout of those two devices to balance the routing within the differential pair and see if it’s possible to generate a cross quad layout. Let’s have a look at one more option, that’s the number of rows. Animate will automatically consider one, two, three, and four-row counts for the devices in this particular differential pair.

Animate will consider all of the different options and work out the permutation that generates the best differential pair layout, considering the requirements of that differential pair and the context in which it is in. Once Animate generates the constraints, the next step is to generate the layouts, which are then shown on the right-hand side of the screen. If we select the differential pair in the schematic, we can cross-probe into the layout.

We want each device of the differential pair to have the same geometrical environment because that means that any process variation or LD effects on the devices can be balanced out. The first step to achieve this is for Animate to place these devices in a regular grid. The second step is that all of the spacings around the differential pair should be identical. So when we look at horizontal spacing, the gap between devices should also be identical. In this case, we’ve only got two rows. If we have more than two rows, then we would want all of those gaps to be identical so that each of the active devices in our differential pair has exactly the same geometrical environment.

Upon selecting our differential pair, we can cross-probe it into the layout.

Polyheads are indicated with little yellow arrows.

In terms of the geometrical environment, we also want the devices to have the same neighbors on the left and the right. In order to achieve that at the end of the rows, Animate has inserted dummy devices for us. These are the light grey devices in the image. These have been automatically inserted by Animate because animate recognizes that we have a differential pair. We also want the poly heads to be identical. If you look closely, you can see the poly head direction is marked by a small circle. All of the devices on the top row have the poly head on the south side, and all of the poly heads on the second row are on the north side of the device.

In order to make sure that each of these devices behaves identically and to counteract process variation across the die, Animate is going to deploy a common centroid layout if possible. If we select just the left-hand device in the schematic, we can see it is straddled, and the second device has got the opposite diagonal, and this means that the average position of those devices is exactly the same. The average position is in the center. In other words, they have a common center of gravity or common centroid. Further than that, thinking ahead in terms of the routing, we want the routing to balance, and therefore Animate has used a cross-quad pattern. Cross-quad is a common centroid by nature, but by having a cross-quad, Animate also has the opportunity to balance the routing, which we’ll see next.

Cross quad common centroid design.

Adding dummy devices to our layout.

We can be reasonably happy with this automatically generated differential pair layout, but there are a few aspects that could be improved. Let’s say we are happy with the horizontal matching that Animate achieved. But vertically, we can see the devices are not matched. The north edge of this device is next to the guard ring. The south edge is also next to the guard ring, but there is a gap. These aren’t not vertically matched yet. This plugin allows us to modify that matching. There are a couple of different ways in which we might want to do that for differential pair. The first option is to add additional rows of dummies above and below the device. We can do that inside Animate using its drag-and-drop interface. We simply select where we want devices, and we can easily add two rows of dummies. And unlike a traditional layout editor, Animate’s editor allows us to not only control the structure of the layout but also it will automatically take care of all of the DRC rules for us. After the process completes, we’ll be back to a DRC clean routed differential pair but with the additional dummies.

Now we have the horizontal matching that we had before and the vertical matching of each device. Animate includes options to reduce the width of these dummy devices if that’s appropriate for your PDK. You can also increase the finger count of the end-of-row dummies. In the example, it is reduced to a single finger, but you can specify an option to say I want the same finger count as the active devices.

An alternative to adding the dummies is to instead have the same guarding reinforcement on each side of the devices, and this can also be done inside Animate’s drag-and-drop editor as well. We can do that by first selecting the guard ring, and we will be presented with numerous anchor points. We then draw reinforcement between any of these anchor points. Animate will again redo the routing and get us back to a DRC clean layout.

Now onto the routing. We are going to use the detailed view so that we can see the routing that animate has considered. We have two objectives with the routing of the differential pair. First, we want any metal that’s above or around the active areas of the devices to be identical. Secondly, we want the parasitics of the left and the right-hand side of the differential pair to be balanced to be the same.

We can use the drag-and-drop tool to draw new guard rings.

Metal one layer is identical on both devices.

We don’t mind so much about what those parasitics are, but we do want them to be balanced. Let’s start by looking at whether the metal is identical for each of the moves. This is the poly for our differential pair, and by cycling through the layers, we can see that metal one, metal two, and metal three for this device are exactly the same.

On metal four is the first we see any routing going over the top of devices, but where we have it gone over the top of devices, the metal is exactly the same for each one of the active devices. Animate has achieved the first objective for a differential pair. Making the metal for each unit to be exactly the same in each of the metal layers.

The next requirement is to balance the routing. So we want the two inputs on the left and the right to balance, and we want the internal routing of the drains to balance. We want the parasitics of those to be identical, and the easiest way to do this is to have identical geometry for both the left and right sides.

The routing on metal four is the same for all the active devices.

We can see the connections on the second and third metal layers.

Now let’s look at the gate connections. These are routed on the second and third metal layers. We can see the cross-quad connections, we can’t exactly match the same layers because we would get a short, but we can see what Animate has done here. By selecting each of the gates, in turn, we can see that the routing is on different layers, but the geometry is identical, width the same width and length, and therefore those two nets are as balanced as they can be.

Ok so, we’ve balanced the parasitics within the differential pair. But the parasitics balancing should not be contained simply within the differential pair. We should also balance what differential pair is connected to as well. And the most common topology is for the differential pair to be connected to a current mirror.

The current mirror has its own matching requirements. We’re trying to make the two legs of the current mirror match the reference. In this case, the diode has been placed in the middle, and the two legs have been placed diagonally around the outside of the diode so that the current mirror itself achieves a common centroid layout. Moreover, Animate is thinking about the interactions between the current mirror and the differential pair. We can see that the tool has arranged the differential pair and the current mirror so that they have a common line of symmetry. They have also been arranged in such a way that the routing is as straightforward as possible between those two structures. In this circuit, M10 connects to M20, and M11 connects to M19, so we can see here that the bottom row current mirror lines up with the top row of the differential pair, and therefore the routing will be as straightforward as possible.

Obviously the particular patterns you need depends on where the current mirror is placed in association with the differential pair. There’s no point coming up with the perfect differential pair layout in isolation because it really does depend on what it’s placed with and where.

Detailed view of the current mirror and differential pair routing.

Here is a high-level view of the placement of the differential pair and its current mirror. Looking at the parasitics from the differential pair and the current mirror, if we select the first leg, we can the routing on the right-hand side here between the current mirror and the differential pair, and if we select the other leg, we can see that it has got the identical symmetrical, balanced shape. The parasitics are not only balanced within the differential pair structure but also between the differential pair and the current mirror. This means the entire structure is balanced.

Okay so so far we’ve just looked at the differential pair and the current mirror, but you might ask if there is additional wiring over to other devices shouldn’t we balance the parasitics of those as well so the entire structure is balanced?

A common way of achieving that requirement is to generate a butterfly-style layout with a vertical line of symmetry. We would then have a left-hand side that exactly mirrors the right-hand side. To achieve this, a common technique is a half-cell where you put half of the devices into one circuit you lay out on the left-hand side and then copy, paste and flip to generate the right-hand side. In Animate, that can be achieved directly without having to generate a half-cell. We can do that by going to the style tab and selecting the mirrored base analog style.

For this style of layout, Animate requires some additional information, it needs to know which of the devices should be on the left-hand side and which devices should be on the right-hand side of the mirror symmetry. However, as with Animate’s other constraints, you don’t need to enter that information manually. Animate will attempt to generate that data automatically and then display it with these red and green colors on the schematic.

Animate style tab for your schematic.

There are various indicators here: a red teardrop means that the device is going to be placed on the left-hand side of the mirror symmetry and a green teardrop means that the device is going to be placed on the right-hand side. These teardrops are joined to indicate that they are symmetric partners. We also have two semicircles; what does that mean? Well, that means that we have an M-factor device and we want to place half of the M-factor on the left and half on the right-hand side. You can see that same symbol on top of the resistors, despite having an M-factor of one. Animate will actually split the resistors into two for us so that the halves can be placed symmetrically. You will note that the match structures have their own color because matches have their own internal symmetric requirements. Animate has now generated numerous new layouts in this new style. If we select the differential pair in the schematic you can see that the differential pair has been placed in the middle on the vertical line of symmetry and then the other devices are radiating away from that central area so that each of the parasitics on on the left are balanced to those on the right for the block. Animate has automatically achieved a butterfly-style layout.

Summary

For optimal differential pair performance:

Channel dimensions of both MOSFETs must be the same.
Placement should be matched, considering LDEs.
Metal should be identical for every MOSFET unit.
Routing should be balanced (R&C) within the differential pair.
Routing between current mirror and differential pair should also balance.
Balancing for the entire block can be achieved with butterfly layout.
With the differential pair placed on a vertical line of symmetry.

Also Read:

Freemium Business Model Applied to Analog IC Layout Automation

Analog IC Layout Automation Benefits

Obtaining Early Analog Block Area Estimates

CEO Interview: Mark Williams of Pulsic

October 17, 2022October 17, 2022

A Perspective on Semiconductor Manufacturing Initiatives & Strategies

A Perspective on Semiconductor Manufacturing Initiatives & Strategies
by Sagar Pushpala on 10-17-2022 at 10:00 am
Categories: Foundries

My name is Sagar, and I’ve been a long-time executive in the semiconductor manufacturing world — holding key positions at large multi-nationals, a leading semiconductor foundry, and partnering with many of the top-tier foundries and OSATs. Since “retiring”, I’ve also spent time advising and investing in start-ups through roles at VCs, incubators, and accelerators. These are my perspectives (and worries) about the industry after working as an insider for 30+ years and more recently as an external board member/observer, advisor, and investor.

On-Shore Fabs

Though the US is racking up some political “brownie points” and allocating tens of billions of dollars of seed capital to create domestic advanced Logic/Memory wafer fabs and manufacturing jobs, I fear it is too little too late. Unfortunately, I don’t believe these seed incentives will be able to sustain cost competitiveness and scale beyond single-factory projects although some companies have announced 10–20 year expansion plans.

In my opinion, the best path forward for Logic/Memory manufacturing and Foundry/OSAT is for the US to ensure that Taiwan and South Korea are politically and structurally stable, such that their semiconductor manufacturing infrastructures will continue to thrive long term.

Intel

Intel’s X86 architecture has likely run out of steam, with little incremental benefits possible without a complete overhaul. AMD, Apple, Nvidia, and Qualcomm will likely bite chunks into their share in the near-term.

To survive, Intel has to decide in short order whether to accelerate and productize competitive wafer fab and packaging technologies to get ahead of TSMC or be completely foundry-dependent. In my opinion, the latter approach could be more prudent.

The Tower-Jazz acquisition has neither the scale nor competitive IP to help Intel outrun TSMC. Instead, I think Intel should acquire Global Foundries and then spin out its Foundry/Packaging functions, creating an independent entity that has a true shot at competing with TSMC. This would be both complementary and meaningful, as it would give Intel a management structure and technology/IP framework to be successful.

Samsung

I believe Samsung Foundry should augment its Advanced Process and Packaging strategy by acquiring UMC and broaden its foundry offerings, providing a similar structure as the Intel-Global Foundries entity I suggested above.

Collectively, such spin-outs and mergers would enable 3 world-class entities (TSMC, Intel + GlobalFoundries, and Samsung + UMC), expanding competition for the semiconductor ecosystem to thrive effectively.

Down Cycle & Over Capacity

Many of the factories sanctioned and being built in new locations will see a significant pullback in loading support over the next 2 years. Optics and investments around this short-term issue have to be managed.

Equipment Supplier Monopoly

The world needs another ASML for Lithography capabilities, especially on advanced nodes (EUV). Its monopoly is stifling growth and billions of dollars’ worth of revenues & capacity are bottlenecked by its inability to ramp to meet demand, let alone get caught up in the China tangle.

China, India & ROW

Rather than trying to create full-fledged competitors and fight the legacy foundry players, China and India should manage to their own strengths, focusing on logical extensions to their regions’ capabilities.

Chinese foundries should continue to drive low-cost manufacturing while focusing on mature technology nodes and consumer products, since many US fabless companies still depend on them today.

The world needs to create another manufacturing hub in India where ‘trusted’ human capital is not constrained. It should double-down on supporting the already thriving high value-add engineering services and product development ecosystem. In particular, a focus on both product definition and associated incubation as well as non-leading-edge manufacturing is long overdue.

To take advantage of recently announced manufacturing incentives and capabilities being sought out in India, top-tier foundries should strongly consider licensing out their breadth of mature technologies to qualified fab operators in 3-way agreements with in-region powerhouses (e.g. TATA, RIL, etc.)

Japan and EU will likely remain US support entities and will continue to be self-sufficient on their initiatives, including attracting top tier foundries into their regions.

Also Read:

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

A Memorable Samsung Event

Does SMIC have 7nm and if so, what does it mean

October 17, 2022March 2, 2023

STOP Writing RTL for Registers

STOP Writing RTL for Registers
by Steve Walters on 10-17-2022 at 6:00 am
Categories: EDA, Semifore

After almost three decades in the EDA business, it is beyond my comprehension to understand why chip designers still hand-write RTL for complex register maps – chip designs with hundreds of registers and thousands of register fields. In today’s silicon world where software is the key to chip-based product success, it is the register map that defines the hardware/software interface (“HSI”) that enables the software stack to bring silicon-based products to life and put a smile of satisfaction on the customer’s face. In the real-world, getting the HSI right is even more important than a few nanoseconds of latency improvement, or a few milliwatts of power savings – if the HSI doesn’t work in the customer environment, you don’t have a deliverable product. So, why do chip development teams still try to manage complex register maps with manual methods? If you want to understand why chip development teams should STOP writing RTL for registers, read on.

The register map specification is created by “company visionaries” who are entrusted to imagine how the product will work in the hands of the customer, and the specification should be a sacrosanct single-source-of-truth HSI specification for all chip development team stakeholders – RTL designers, the verification team, the software team, and documentation. All team stakeholders should strictly adhere to the HSI specification – and observe a disciplined process for negotiating changes to the HSI when necessary.

The RTL should faithfully implement every nuance of the HSI specification because the slightest infidelity can be catastrophic (read “expensive”), and the software team must be pro-active participants in the RTL implementation to enable the richest possible customer experience. And yes, finalizing the HSI is an iterative process, sometimes extending beyond product delivery – so changes to the HSI implementation must be fast, accurate, comprehensive, and include all chip team stakeholder views. Human intervention only adds risk, consumes precious resources, and will assuredly impair productivity.

YES, Register Map RTL Is Different

In today’s silicon world, chip implementation is a composition of processor cores, memory blocks, third-party IP, and bespoke RTL – the RTL where a company adds “secret sauce” based on experience and proprietary innovation. It’s challenging to produce a compellingly differentiated chip-based product solely from commercial IP blocks – but it’s no longer economically feasible nor efficient to re-create everything from scratch. Which should lead chip developers to focus their efforts on unique architectures, unique data flows, selecting optimal third-party IP, the bespoke RTL, and design tool automation – and NOT “waste” design team resources where there is no differentiated value-add.

Register map RTL is different, it should be afforded special attention in the design flow for complex register maps, and because fidelity of the single-source-of-truth specification is so crucial to a successful chip project, this RTL implementation should be fully automated. Only with full automation can complex register map RTL be managed successfully for today’s silicon development –– production-proven, comprehensive register management tools that automate the generation of all register map views. This is NOT the place to bet-the-farm on non-scalable, hacked together spreadsheets and scripts.

Do Yourself and Your Company a Favor – Start with A Domain-Specific Register Map Specification Language

There’s a lot of confusion and misinformation about register map specification languages. This is the language or format used to capture the detailed register map requirements – that becomes the single-source-of-truth HSI specification.

Popular data formats like IP-XACT, and JSON were developed as data exchange formats – they were NOT developed for authoring register map specifications. They were NOT purposely developed to express the many different, sometimes subtle, property nuances of modern complex register maps. Maybe better than spreadsheets, but non-optimal for complex register maps.

SystemRDL is a register map authoring language that was originally developed for internal use by Cisco Systems specifically for register map specification, commercialized and branded as “SystemRDL” by Denali in 2006, the specification for which was published by the SPIRIT/Accellera consortium in 2009. The last SystemRDL update (SystemRDL 2.0) was released in 2017, and according to the Accellera website (https://www.accellera.org/activities/working-groups/systemrdl) – “This Accellera working group is currently inactive.” SystemRDL is still in use today, but is missing significant market-driven requirements for register map specification.

There is only one commercial, domain-specific register map authoring language available today that was purposefully developed for specifying complex register maps and address the feature deficiencies of SystemRDL 2.0, that has advanced to keep pace with today’s chip development needs – CSRSpec from Semifore. It is easy to learn and use, is rich in register property expression features, is scalable to millions of registers, and is silicon production-proven over the past 16 years by leading silicon developers around the world.

Automate Register Map View Generation for All Chip Development Stakeholders – Including the RTL.

Once you have settled on a scalable language for your single-source-of-truth specification – let automation do the rest. There are several register map “views” that are essential for chip project success – RTL (Verilog, VHDL), verification (UVM), software (C-header files), and documentation (Word). And it is essential that all views stay in sync throughout the chip development cycle – sometimes after product delivery. The generation of these register map views is not the place to invest precious engineering resources, so automation is the obvious solution. Automation eliminates human error and reduces the development teamwork-effort – so delegate this part of the design flow to automation tools.

CSRCompiler is a cross-compiler from Semifore that accepts register map specifications in multiple input languages/formats – CSRSpec, SystemRDL 2.0, IP XACT, and spreadsheets – and generates all the required register map views – RTL, UVM, IP XACT, C-headers, and Word documentation.

Final Comments

Now – if you agree with the preceding, why would RTL designers want to, or even be allowed to, hand-write RTL for complex register maps? Could it simply be because that’s the way it’s always been done? Could it be because of a lack of awareness that a better way is available? Could it be because changes to the design flow are hard, and everyone is so busy that they think there’s no time to change the design flow? If there’s any doubt about the complexity of future register maps – they will only become increasingly more complex!

Whatever the reason, you should consider contacting Semifore for a demonstration of a better automated solution to manage your complex register map implementations. Now you know why chip development teams should STOP writing RTL for registers.

Also Read:

Semifore is Supplying Pain Relief for Some World-Changing Applications

Webinar: Semifore Offers Three Perspectives on System Design Challenges

A Solid Methodology is the Margin of Victory

October 16, 2022March 26, 2023

Chip Train Wreck Worsens

Chip Train Wreck Worsens
by Robert Maire on 10-16-2022 at 4:00 pm
Categories: China, Semiconductor Advisors, Semiconductor Services

-Semi Equip go from bad to worse as TSMC cuts capex
-Numbers will be slashed for December quarter
-So far just a handful of exceptions to blockade but temporary
-China’s response could be very ugly

Fast motion train wreck

Just when some people thought that Fridays department of commerce announcement couldn’t get worse, TSMC reports a good quarter but cuts capex.

This means that not only will chip equipment companies lose much of their biggest market, China but also see their largest customer, TSMC, cut spending at the same time. This is on top of cuts from Micron, Intel and others.

This is perfect storm material….

From famine to feast and feast to famine overnight

The chip side of the market has gone from famine (shortage of chips) to feast (a glut of chips) as the economy has hit the brakes on demand.

The semiconductor equipment industry has gone from feast (backlog out the door and more orders than they could handle) to famine (with their largest market cut off overnight and largest customer cutting spend).

It is the rapidity of all this that will make heads spin and valuations collapse.

Even though these issues came on virtually overnight they are going to take a very, very long time to adjust to and there really isn’t a good way to fix them other than let time play them out.

The glut will take time to be absorbed and it will take a very long time for other regions to make up for what China has been buying to expand capacity.

Is the China embargo the solution to the glut?

In a perverse way, the embargo on equipment sales to China will obviously slow the flow of chips out of China and could work to reduce the excess supply that many, including TSMC, are worried about.

We have seen before, in the case of Jin Hua, when US companies leave overnight the fabs come to a halt for lack of support.

Of course, the fabs will try to keep going but will start to unravel without spare parts, service and upgrades very quickly.

A short reprieve from China Sanctions

A number of chip companies that are not China domiciled have gotten a 1 year reprieve in which they can still obtain equipment and parts for their China operations. Among them is TSMC, announced on their call last night. The bigger question is will the reprieve be extended a year from now or will that be the end of the line?

If I were a non Chinese company with an operation in China I would be wondering if its time to “get out of Dodge” before things got worse….
Maybe I won’t put more money into China because of an uncertain future.
All this makes fabs in the US and anywhere but China look very attractive.

So far it appears the bleeding edge is targeted

So far, from what we have been able to determine, the sanctions appear to be focused as announced on leading edge technology.

There is still a lot of dust to settle but leading edge is certainly a big percentage of the most profitable business for most companies.
Things will likely come down to a case by case basis with the intended customer likely playing a big part of whether a license would be approved.

Payback from China?

We have spoken previously at length about the role that rare earth elements play in the electronics industry. Everything from coatings on dep and etch chambers to batteries for cars. It’s not that China has the only rare earth elements on the planet it’s that they are cheap to the point where mines and other sources in the US and elsewhere couldn’t compete.

China could easily cut off rare earth elements, especially those used in the semiconductor industry and it would take a very long time to find alternate sources.

Just as important are sub-assemblies made in China. One example is the plethora of products that comes out of Shenzen. As an example, Advanced Energy (AEIS) makes RF and DC power supplies for the semiconductor equipment industry in China and China could halt the export and shut down a big piece of Applied’s and Lam’s business to other countries.

A US equipment manufacturer recently told suppliers that it was still OK for them to ship sub-assemblies out of China for use in US made tools (until China cracks down on that).

The bottom line is that China is a big part of the supply chain for US semiconductor equipment tools and could cause a lot of damage and halt other production Payback is a B…..

Smaller players will get shut out as industry contracts

As demand for chips slows down, TSMC will recapture all that business that was overflow and “allowed” second and third tier fabs to get because they couldn’t handle it. TSMC will want to keep its fabs operating near 100% capacity and will mark to market to get that to happen.

Companies like Global Foundries which only turned a profit when demand went crazy are the most vulnerable in a glut when customers run back to TSMC. Contracts won’t matter.

The stocks

The stocks will bounce around quite a bit depending upon that days news flow.
We would expect a significant downdraft when companies take a significant haircut to their projections for the December quarter. We see 20% or so revenue cuts in some cases.

Obviously a lot of hot air has come out of what were overheated chip stocks making the valuations look more attractive but it’s clear that there is more bad news to come. Uncertainty will remain and the outlook for 2023 is clearly for a down year, it’s just a question of how far down.

We are likely to see some short-term rallies or dead cat bounce blips but the overall vector remains on a downward trend.

We have been covering the space longer and been involved with more transactions than any other financial professional in the space.

We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.

We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Semiconductor China Syndrome Meltdown and Mayhem

Micron and Memory – Slamming on brakes after going off the cliff without skidmarks

The Semiconductor Cycle Snowballs Down the Food Chain – Gravitational Cognizance

Podcast EP113: How Samtec is Enabling AI Growth in the Cloud and at the Edge with Matt Burns

Podcast EP113: How Samtec is Enabling AI Growth in the Cloud and at the Edge with Matt Burns
by Daniel Nenni on 10-14-2022 at 10:00 am

Dan is joined by Mattew Burns, Matt develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries.

Dan and Matt discuss the recent AI Hardware Summit – how the conference has grown and the areas of high-growth applications. Matt discusses the overall ecosystem for AI hardware system design and explores Samtec’s role in catalyzing new innovation through collaboration and technology leadership in the high-performance data communications area.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

October 14, 2022August 2, 2023

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview
by Daniel Nenni on 10-14-2022 at 6:00 am
Categories: Events, Foundries, TSMC
5 Comments

One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.

In my 40 years as a semiconductor professional I cannot think of a more exciting time for our industry and TSMC is one of the reasons why. The ecosystem they have built is a force of nature that may never be replicated in the semiconductor industry or any other industry for that matter. Hundreds of thousands of people all working together for a common goal of silicon that could change the world!

The guest speaker for the Silicon Valley event will be none other than Jim Keller of Apple, AMD, Tesla, and Intel fame. Jim is an amazing speaker so you definitely do NOT want to miss this one.

REGISTER NOW

Learn About:

Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies
Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications
Updated design solutions for specialty technologies enabling ultra-low voltage, analog migration, mmWave RF, and automotive designs targeting automotive and IoT designs
Ecosystem-specific TSMC reference flow implementations, P& R optimization, machine learning to improve design quality and productivity, and cloud-based design solutions
Successful, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers

For more information on the TSMC OIP Ecosystem Forum, e-mail us at: tsmcevents@tsmc.com.

Here is the agenda as of today:

Time	Plenary Session
08:00 – 09:00	Registration & Ecosystem Pavilion
09:00 – 09:15	Welcome Remarks
09:15 – 10:10	Enabling System Innovation & Guest Speaker
10:10 – 10:30	Coffee Break & Ecosystem Pavilion
	TSMC Technical Talks
10:30 – 11:00	TSMC N3E FinFlex™ Technology: Motivation, Design Challenges, and Solutions TSMC	TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity TSMC	TSMC Analog Migration Talk TSMC
	HPC & 3DIC Track	Mobile & Automotive Track	IoT, RF & Other Track
11:00 – 11:30	GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends GUC	Analog Design Optimization by Integrating MediaTek’s ML-based Engine within the Virtuoso’s Analog Design Environment MediaTek / Cadence	Synopsys / Ansys / Keysight mmWave Reference Design Flow on TSMC N16FFC Synopsys / Ansys / Keysight
11:30 – 12:00	A Unified Approach to 3DIC Power and Thermal Integrity Analysis Through TSMC 3Dblox Architecture and Ansys RedHawk-SC Platform Ansys	Achieving Best Performance-per-Watt at TSMC’s N2 and N3E Hybrid-Row Process Technology Nodes using Fusion Compiler and the Fusion Design Platform Synopsys	Breakthrough platform for AIoT markets Dolphin Design
12:00 – 13:00	Lunch & Ecosystem Pavilion
13:00 – 13:30	SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Datacenter, 5G and AI applications eTopus Technologies / Siemens EDA	An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis Synopsys / TSMC	Cadence mmWave Solutions Support TSMC N16 Design Reference Flow Cadence
13:30 – 14:00	Advanced Assembly Verification for TSMC 3DFabric™ Packages Broadcom / Siemens EDA	Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study Synopsys	Analysis of Design Timing Effects of Threshold Voltage Mistracking between Cells Synopsys
14:00 – 14:30	Simplifying Multi-chiplet design with a unified 3D-IC platform solution for 3Dblox technology Cadence	Low power high density design implementation for AI chip Hailo Technologies / Siemens EDA	RISC-V is delivering performance and power efficiency from Embedded to Automotive to HPC SiFive
14:30 – 15:00	Advanced Auto-Routing for TSMC^® InFO™ Technologies Cadence	Reliable compute – taming the soft errors Arm	TSMC, Microsoft Azure and Siemens EDA Collaboration – Enabling Your Jump to N3E using the Cloud and Calibre nmDRC Siemens EDA / Microsoft
15:00 – 15:30	Coffee Break & Ecosystem Pavilion
15:30 – 16:00	3D System Integration and Advanced Packaging for next-generation multi-die system design using Synopsys 3DIC Compiler with TSMC 3DBlox and 3DFabric Synopsys	Self-testing PLLs for advanced SoCs Silicon Creations	HPC & Networking Trends Influencing High-Speed SerDes Requirements Synopsys
16:00 – 16:30	TSMC 3DBlox Simplifies Calibre Verification and Analysis Siemens EDA	Cadence Cerebrus AI driven design optimization pushes PPA on TSMC 3nm node Cadence	Integration Methodology of High-End SerDes IP into FPGAs based on Early Technology Model Availability Achronix / Alphawave IP
16:30 – 17:00	GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms proteanTecs	Kick-off your design success with Automated Migration of Virtuoso Schematics Cadence	Pinless Clocking and Sensing Analog Bits
17:00 – 17:30	Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs – Challenge Accepted Alchip / Synopsys	Delivering best TSMC 3nm power and performance with Cadence digital full flow Cadence	Understanding UCIe for Multi-Die Systems Leveraging CoWoS and Substrate Packaging Technologies Synopsys
17:30 – 18:30	Networking and Reception

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Abut TSMC

TSMC (TWSE: 2330, NYSE: TSM) created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 535 customers and manufactured more than 12,302 products for various applications covering a variety of end markets including smartphones, high performance computing, the Internet of Things (IoT), automotive, and digital consumer electronics.

Annual capacity of the manufacturing facilities managed by TSMC and its subsidiaries exceeded 13 million 12-inch equivalent wafers in 2021. These facilities include four 12-inch wafer GIGAFAB® fabs, four 8-inch wafer fabs, and one 6-inch wafer fab – all in Taiwan – as well as one 12-inch wafer fab at a wholly owned subsidiary, TSMC Nanjing Company Limited, and two 8-inch wafer fabs at wholly owned subsidiaries, WaferTech in the United States and TSMC China Company Limited.

In December 2021, TSMC established a subsidiary, Japan Advanced Semiconductor Manufacturing, Inc. (JASM), in Kumamoto, Japan. JASM will construct and operate a 12-inch wafer, with production targeted to begin by the end of 2024. Meanwhile, the Company continued to execute its plan for an advanced semiconductor fab in Arizona, the United States, with production targeted for 2024. www.tsmc.com

Also Read:

Future Semiconductor Technology Innovations

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Process Technology Development

October 13, 2022July 15, 2024

The CHIPS and Science Act, Cybersecurity, and Semiconductor Manufacturing

The CHIPS and Science Act, Cybersecurity, and Semiconductor Manufacturing
by Simon Butler on 10-13-2022 at 10:00 am
Categories: EDA, Perforce

This year is proving to be a momentous one for U.S. semiconductor manufacturing. During a global chip shortage and record inflation, President Biden signed into effect the CHIPS and Science Act – which so far is the greatest boon to U.S. semiconductor manufacturing in history, with $52 billion in subsidies for chip manufacturers to build fabrication plants in the U.S.

The CHIPS Act seems like a green light for domestic manufacturing. However, another piece of legislation passed earlier in the year may be a stumbling block for semiconductor design shops eager to serve national security projects. Enter Executive Order 14028, “Improving the Nation’s Cybersecurity.”

Rolled out several months before the CHIPS Act was signed, this Executive Order defines parameters that will force U.S-based software companies to change long-established development and design processes if they want to comply with federal regulations regarding information-sharing between the government and the private sector.

Here we examine how these two pieces of legislation relate, what they mean for semiconductor companies, and why the highs and lows of American semiconductor manufacturing boil down to one thing: security.

Protect Your IPMethodics IPLM is the single source of truth for all your chip IP. See how you can protect your team’s IP from design through verification.

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The CHIPS and Science Act of 2022

The CHIPS and Science Act of 2022 provides $52 billion in subsidies for chip manufacturers to build fabrication plants in the U.S. For reference, currently only 12% of all semiconductor chips are made in the U.S.

This Act comes amidst a global economic downturn, with lawmakers hoping that American-made chips will solve security and supply chain issues. In short, this is something the U.S. needs to reassert its historical influence on semiconductor manufacturing.

Security Considerations

One of the biggest considerations, and benefits, to domestic-made semiconductors is national security. Recent geopolitical instability has caused concern over potential IP leakage and theft. For the U.S. Department of Defense (DoD), it is imperative to have a secure and trusted ecosystem for the design and manufacture of semiconductors. But with most of today’s manufacturing done overseas, the DoD have had major challenges executing their national security-related projects.

The automotive industry is another area that will benefit from a trusted domestic ecosystem and a more resilient supply chain. As we progress towards autonomous vehicles, compromised components could be used by malicious parties to take control of the system and cause damage and injury.

In these cases (and others), it’s clear that there is a need for component and IP provenance, along with geofencing, to reduce the likelihood of security breaches. More competitive and accessible domestic manufacturing can help solve this by keeping sensitive IP within the borders of the U.S.

Executive Order 14028: “Improving the Nation’s Cybersecurity”

The Executive Order on cybersecurity stemmed from recent data breaches, with the attempt to patch vulnerabilities in sharing between the private sector and the U.S. government. For companies, this means a brighter light will now be shone on security throughout the embedded software development process. For developers, this signifies a greater need to maintain visibility into their code and keep track of any vulnerabilities throughout the lifecycle.

To tackle this, a number of recommendations/requirements have been put forward by this Executive Order, including better defined processes around cyber security incidents, a higher level of awareness around permissions (“Zero Trust”) and the concept of a Software Bill of Materials (SBOM), which should be delivered as part of the software implementation to enable higher levels of traceability and provenance.

This SBOM should enable system integrators to understand their exposure to security concerns in delivered code via documentation of the software versions delivered, their provenance, and the originating supply chain source, all of which allow for better traceability in the design.

The Unified BOM

An SBOM will take the form of a hierarchical tree of components where each component includes the versioned implementation and important metadata that infer its state, license, compliance with standards, and other pieces of data. This SBOM should be in machine-readable format for integration into development and test traceability methodologies.

In short, the SBOM should be a complete manifest of the software delivered with the project and its current state. With the advent of IP-centric design practices in the semiconductor space, we have already seen widespread adoption of the hardware BOM (HBOM) that records the IP component versions that implement an SoC and material metadata.

Since a large portion of today’s SoCs include an embedded software component, this new governmental SBOM requirement suggests SoC developers should be managing the unified platform SBOM/HBOM as part of the development life cycle, and in some cases delivering with the final product shipment to facilitate traceability and threat detection in the target system integration.

The “Unified” BOM: A Complete Software/Hardware Manifest

The U.S. government has started two important initiatives with the CHIPS and Science Act and Executive Order 14028. The CHIPS Act will revitalize U.S.-based semiconductor manufacturing to secure the domestic semiconductor supply chain and mitigate concerns with national security related designs, while Executive Order 14028 enforces software development practices that reduce the likelihood of cyberattacks.

Software needs hardware to run and understanding the interdependence of software and hardware is important. By applying the SBOM mandate to the entire system on a chip (SoC) manifest with a unified software/hardware BOM, we can help to ensure that the best practices outlined in the Executive Order will be applied to the entire component tree for a given SoC.

This is something that many companies have started to adopt anyway, independent of any government initiative. Although, Executive Order 14028 now mandates this as a requirement to be able to engage in DoD software development projects. One could argue that without a complete BOM to reflect the full set of software and hardware components in an SoC, we’re not fully addressing provenance and security issues in the design.

Wrap-up: Improving Cybersecurity Through Secured Supply Chain

In summary, the hope is that the $52 billion CHIPS Act will help mitigate the supply chain bottleneck plaguing the semiconductor industry. By combining secure manufacturing with secure development best practices, we have a much higher likelihood of improving our semiconductor supply chain and providing a trusted source of components for our national security projects.

Leverage CHIPS Funding With Methodics IPLM

Methodics IPLM provides a scalable IP lifecycle management platform that tracks IP and its metadata across projects, providing end-to-end traceability, and facilitating IP reuse. With a tool such as Methodics IPLM in hand, companies can setup the infrastructure called for by the CHIPS Act and smooth the transition to state-of-the-art U.S.-based semiconductor manufacturing.

Connect with Perforce IP experts to learn more about Methodics.

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Originally published on Perforce.com blog.

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October 13, 2022October 16, 2022

VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies

VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies
by Kalar Rajendiran on 10-13-2022 at 10:00 am
Categories: IP, Semiconductor Services, VeriSilicon

The tremendous growth in edge devices has focused the spotlight on Edge-AI processing for low latency, low power and low-DDR bandwidth compute needs. Many of these Edge-AI applications depend on effective and efficient processing of image and video streams which in turn relies on computer vision technology. In early September, VeriSilicon announced the launch of AI-ISP, an innovative AI image enhancement technology that the company claims that it can surpass what traditional computer vision technologies offer. The company credited its Glass to Glass (from camera-in to display-out) intelligent pixel processing IP portfolio and its innovative FLEXA™ IP interconnection technology for this achievement. This blog will look into the nuts and bolts behind that claim.

About VeriSilicon

Many may already be familiar with VeriSilicon but a refresher will serve well as a backdrop for this blog. From more than two decades ago when the company started as a design service and a turnkey service provider, VeriSilicon has expanded and evolved a lot as well. The company is committed to providing customers one-stop custom silicon solutions through its silicon services and IP licensing services of in-house semiconductor IP. Customers benefit from its “Silicon Platform as a Service (SiPaaS®) model that enables design efficiencies and higher quality while lowering product risk and development costs. VeriSilicon can create custom silicon products from definition to test and package within short cycle times.

The company has delivered a variety of custom silicon solutions supporting applications such as high-definition audio, video, high-end processing, video surveillance, IoT connectivity, smart wearable, and many others. It leverages an in-house IP portfolio of more than 1,400 analog and mixed-signal IPs and RF IPs along with processor IPs. Its processor IPs fall into the following main types: GPU, NPU, VPU, DSP, ISP and Display Processor, plus VeriSilicon FLEXA™ IP fusion technology.

AI-ISP Technology

Under its platform model, VeriSilicon continues to fuse multiple technologies to address the industry challenges by breaking the limit of the traditional approaches. The VeriSilicon AI-ISP technology is a result of such a push to support the Edge-AI processing domain. The technology combines VeriSilicon’s Neural Network Processing (NPU) technology with its Image Signal Processing (ISP) technology to deliver innovative image quality enhancement for computer vision. The AI-ISP is built on an intelligent workload balancing architecture that optimizes power consumption and memory access. It is built for applications that demand ultra-low power consumption under near-zero illuminance conditions. VeriSilicon’s AI-ISP can be leveraged to benefit smartphones, automotive electronics, surveillance camera systems, and Industrial Internet of Things (IIoT) among many other applications.

AI-ISP Leverages Already Proven Technologies

VeriSilicon develops its various IPs with the SiPaaS model in mind. Its various IP technologies support each other to deliver enhanced results. For example, its Image Signal Processing (ISP) IP focuses the target area to obtain a clearer image and set things up for its Network Processing Unit (NPU) to perform detection and recognition functions. On the other hand, its NPU is capable of performing dark light, noise reduction during the ISP processing, for further enhancement of image quality. Following are the underlying technologies that the AI-ISP offering leverages.

VeriSilicon FLEXA™

VeriSilicon’s FLEXA™ is an innovative, low-power and low latency interface communication technology that allows ISPs to read, write and access data directly from the NPU. The FLEXA API is built around a hardware and software protocol that enables efficient data communication between multiple pixel processing IP blocks. Systems built with FLEXA compliant IPs can leverage the API to run AI applications to reduce DDR traffic and achieve low pixel processing latencies.

Image Signal Processing (ISP) Technology

VeriSilicon’s ISP technology is already market proven through customer adoption of various cores from its ISP product portfolio.

It’s worth mentioning that VeriSilicon’s ISP8000L-FS V5.0.0 has achieved both ISO 26262 and IEC 61508 functional safety standards, which is the company’s first IP that aligns with dual international functional safety standards. The ISP8000L-FS V5.0.0 is designed for advanced and high-performance camera-based applications, which supports dual cameras with single 4K@60fps or dual 4K@30fps video capturing. It also integrates HDR (High Dynamic Range) processing, 2D/3D noise reduction technologies, and built-in functional safety mechanisms. The ISP8000L-FS V5.0.0 has been certified by both ISO 26262 and IEC 61508 functional safety standards, which marks a significant milestone in VeriSilicon’s expansion of its functional safety IP portfolio. Adopting the certified ISP IP will help customers accelerate their product development process with reduced risk of systematic failures and random hardware failures in safety-critical automotive and industrial applications.

To read the press announcement, go here.

Neural Network Processor (NPU) Technology

VeriSilicon’s NPU technology is already market proven through customer adoption of various cores from its NPU product portfolio. It incorporates self-adaptive resolution calculation and multi-frame fusion function, as well as excellent noise reduction performance even in low light conditions. The technology comes with a complete software stack and software development kit (SDK) that supports deep learning frameworks including Tensorflow, PyTorch, ONNX, TVM, and IREE. For the specific cores that support various applications from IoT and Wearables to Automotive and Data Centers, refer to the Figure below.

Summary

As a SiPaaS company, VeriSilicon continues to bring valuable IP cores and integration services to benefit its customer base. Customers are enabled to implement efficient, low-power integrated solutions that can perform beyond the limitations of traditional approaches. Its customer base covers consumer electronics, automotive, computer and peripheral, data processing, IoT and other applications.

To learn more about VeriSilicon, visit their website.

To read the press announcement about AI-ISP, go here.

October 13, 2022March 26, 2023

Semiconductor China Syndrome Meltdown and Mayhem

Semiconductor China Syndrome Meltdown and Mayhem
by Robert Maire on 10-13-2022 at 6:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services
3 Comments

-Commerce Dept drops a 100 page nuke on the Semi industry
-Many words but not a lot of clarity on exact impact
-Implementation & interpretation will be key to quantify impact
-It’s all bad, just a question of how bad

China is the industry’s biggest customer

We all know that China uses most of the world’s semiconductors but certainly does not produce enough internally to satiate that need. China buys $300B+ of semiconductors and is the worlds largest buyer of semiconductor equipment.

On the equipment side China produces very little equipment and imports the vast majority from the US, Japan, The Netherlands, Korea and other countries.
Restricting China’s access is a huge impact on the global market in both directions akin to an oil embargo but even worse.

It is also akin to going from an economic cold war to a hot, live war.
It is also unclear how much is real and how much is posturing much like Russia’s posturing on nuclear weapons.

It could be the US sending a message to China regarding Taiwan, that its not kidding and will take off the gloves to prove it.

Cutting China out of the semiconductor industry is a lot like cutting Russia out of the global economy.

What reaction does this provoke? An escalation or negotiation?

Much of China’s prosperity is linked to both doing business with the US as well as producing increasingly technical goods with advanced semiconductors and this could attack both.

Does China get pissed off and decide to encircle Taiwan? Does China back off and perhaps not support Russia as much? Does that even matter if the US is serious about crippling China’s effort in semiconductors.

In our view we don’t see the US backing away but the US could modulate how strictly it enforces potential restrictions depending upon China’s reaction.

Its open to implementation

The commerce department document issued on Friday is huge, 100 pages long. It says a lot but there is a lot more that it doesn’t say and it is unclear in many instances how to interpret what is said.

Link to Commerce China Semiconductor Document

Back to the future

As we have pointed out many, many times in past notes, licensing of semiconductor technology is not new at all. We recall over 20 years ago when we worked on China’s SMIC IPO that China was restricted to N-2 in technology (staying two technology nodes behind) . Over time that restrict faded away but China remains roughly two or mores nodes behind just due to market forces and speed.

The US government is just putting into rules, what exists already in the market today and what existed in the past…this is far from the earthquake that investors and analysts imply that it is. However, the definitive announcement is what has made the difference in perception.

14NM is a very fuzzy line- its not a binary decision

Semiconductor equipment that can be used to make 14NM chips is a very broad definition….

It can include equipment and technology decades old or the definition could be very limited to litho related equipment that defines line width.
The implementation could be limited to process equipment which actually makes the 14NM lines or grow to include metrology and inspection equipment which measures and controls the process tools.

It is unclear from the document how far and wide a net the commerce department will cast in covering both equipment and chips themselves.
In building a super computer its not just advanced CPU and GPUs that are needed but lots a generic glue that binds the whole system together.

Thus the Department of Commerce has an infinite amount of latitude and discretion to implement the new rules and we have no idea on which end of the spectrum they will come down

The stock market hates uncertainty and we have a huge amount

Perhaps the main reason that the semiconductor stocks have cratered so badly is the amount of uncertainty caused by Friday’s release.

We simply don’t know and won’t know for quite a while how this will be implemented. Anyone who says they know the exact impact on the industry is lying. We can speculate as to the range of potential impact but that could range from little to no impact all the way to a virtual ban on doing any business at all with China in the semiconductor industry, and everything in between. Somewhere in between is obviously the right guess.

We just won’t know, and neither will the companies know until licenses are either approved or denied, so its going to take months to get a handle on the actual impact. The only thing we know is that it will be negative but not how negative.

Meanwhile, while we are in the throes of uncertainty the stocks will behave badly as we have already seen.

This should not be a surprise as it was long in coming

We have been both writing about and publicly speaking about the US versus China in the semiconductor industry for 7-8 years now, longer than anyone we know of and writing more about it. We were perhaps a little ahead of reality buts its not like this issue has sprung up out of nowhere. Sooner or later the US had to do something or watch China eat its lunch in yet another critical industry, with semiconductors perhaps being the most critical industry of all given the defense and intelligence aspects

This does not force China’s hand on Taiwan

As we have said before, we are sure that China well understands that taking Taiwan by force would result in the decimation of semiconductor capacity there and would be a very hollow victory. China has no choice but to peacefully embrace Taiwan. If not , the fabs would stop working in a few weeks due to lack of critical support from foreign equipment vendors, that is assuming that the fabs were captured undamaged and satchel charges of C4 were not left behind under $150M litho tools.

So we don’t see this new rule making pushing any agenda on Taiwan. The status quo still exists

The stocks

We have been clearly negative on the group for the past over 9 months and have sited China as an additional risk on top of the general economic risk. All the risk factors are far from over. We have not bottomed in the economy or the semiconductor cycle. The semiconductor down cycle just started a few months ago. We won’t know the impact of this new China department fo commerce policy for several months and quarters reporting.

The only assumption we can make is negative.

As we have also said before, we would avoid value traps…. the stock is down XX% and too cheap to ignore or similar refrains.

We have no visibility on a turn and certainly no turn in fortunes in what’s left of 2022. 2023 certainly looks like a significantly down year versus 2022, but we don’t yet have a handle on how far down.

Part of the issue remains that the semiconductor industry has been so strong for so long that it may take time for investors to adjust to something other than just a blip of bad news….this is clearly more than a blip…..

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus

Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
by Daniel Nenni on 10-12-2022 at 10:00 am

Dan is joined by Brandon Bautz, Sr. Group Director of Product Management, responsible for the Cadence silicon signoff and verification product lines in the Digital & Signoff Group.

Dan and Brandon explore the substantial challenges faced by design teams needing to perform full-chip signoff at an accelerated pace for advanced nodes. Brandon details the unique capabilities of Certus and how it addresses the challenges customers face, making full-chip signoff far more efficient and predictable.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.