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Altair’s Jim Cantele Predicts the Future of Chip Design

Altair’s Jim Cantele Predicts the Future of Chip Design
by Mike Gianfagna on 07-25-2023 at 10:00 am
Categories: AI, Altair, EDA

Altair’s Jim Cantele Predicts the Future of Chip Design

We all know chip design is changing in substantial ways and at a fast pace. The demands being placed on semiconductor systems are growing dramatically, and the innovation being delivered to address those demands is just as dramatic. Everyone seems to have an opinion on these trends, and a set of predications to make sense out of it all. A recent Executive Insight on this topic caught my eye. The company publishing the piece is at the epicenter of many relevant trends. And the author is someone I know has been on the front line of change for many years. This is a must-read piece. Before I provide a link, I’ll whet your appetite a bit about how Altair’s Jim Cantele predicts the future of chip design.

The Company

Altair is a broad-based technology company that sits at the crossroads of many of the relevant trends that are changing the world around us. The company delivers comprehensive, open-architecture solutions for data analytics & AI, computer-aided engineering, and high-performance computing.

Its key goals include enablement of design and optimization for high performance, innovative, and sustainable products and processes against the backdrop of a highly connected world.

If we focus on chip design, Altair semiconductor design solutions are built to optimize EDA environments and to improve the design-to-manufacturing process, eliminate design iterations, and reduce time-to-market. The company provides tools that address the challenges of ever-increasing performance requirements and product complexity from chips to PCBs, and embedded systems, all the way to product realization.

You can learn more about Altair’s pedigree in this area here.

The Author

Jim Cantele

Jim Cantele wrote the piece. He is the Global SVP of Sales and Technology at Altair. Once upon a time, I worked with Jim at a small DFM startup. We were breaking new ground there, and Jim has been doing that his whole career.

Jim has seen the demands of innovation up close at large enterprises such as Mentor Graphics and Cadence Design Systems. He also pushed the envelope at high-profile startups such as One Spin Solutions, Celestry, and Runtime Design Automation, which was acquired by Altair six years ago.

Jim has seen a lot and his opinions on the future of chip design are worth listening to.

The Predictions

The Executive Insight discusses five semiconductor design trends. Taken together, they tell a compelling story. You need to hear Jim’s views directly, but here is a summary of the trends discussed.

#1: Reaching for the Sky: When you run out of room in two dimensions, you move up. Architects have known that for years, and the concept is quite relevant for chip design. But things aren’t as simple as they seem with an approach like this.

#2: Bringing Design In-House: Many factors conspired to create the chip shortage we are all too familiar with today. One impact of this situation was bringing chip design in-house to control your own destiny.  This trend created many challenges, and companies still struggle to make the ideas of in-house design work today.

#3: Designing in the Cloud: Cloud computing is clearly here to stay. But using the vast resources available for efficient and cost-effective chip design isn’t as easy as it seems.

#4: Artificial Intelligence and Machine Learning: AI and ML are everywhere. This is clear. The compute and memory demands of these technologies puts a huge strain on chip design.  What have we learned from AI and ML that can be applied to solve these design problems?

#5: Technology Convergence: The blurring of lines between different computing approaches and different architectures presents both a huge opportunity and a substantial challenge for chip design. How will this all come together? And are the solutions already here?

To Learn More

I encourage you to read the Altair Executive Insight. It will help to make sense out of a rapidly changing world. You can check out the piece here to learn how Altair’s Jim Cantele predicts the future of chip design.

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Convergence Between EDA and MCAD and Industrial Software

Convergence Between EDA and MCAD and Industrial Software
by Bernard Murphy on 07-25-2023 at 6:00 am
Categories: Cadence, EDA
1 Comment

convergence eda mcad etc min

Cadence hosted a panel at DAC on how EDA, MCAD and industrial software have come together, a topic I always find interesting. Many years ago, I worked on a NAVAIR contract bid team, an eye-opener for a young engineer who thought that innovation started and ended with electronic design. I remember CATIA (3D modeling) being a component in the bid, along with PLM and other automation outside the EDA realm. This naturally made me wonder about the interaction between these domains. Back then, there wasn’t much interaction that I remember. This panel provided a useful update on what has changed.

The panel was moderated by Jay Vleeschhouwer (Managing Director at Griffin Securities) and included John Lee (GM/VP of the Electronics, Semiconductor and Optics Business Unit at Ansys), Tom Beckley (Sr. VP/GM of the Custom IC and PCB Group at Cadence), Brian Thompson (Division VP/GM of CREO and Desktop Engineering Calculations at PTC), Stephane Sireau (VP of High Tech Industry for Dassault Systèmes), and Tony Hemmelgarn (President and CEO of Siemens Digital Industries Software). These executives represent a comprehensive span of automation and lifecycle management across systems design. In some areas, each offers unique advantages, in others they compete, sometimes they cooperate. As usual in my panel write-ups, I’ll summarize my takeaways.

What motivates convergence?

Back in my NAVAIR days the boundaries between electrical CAD, mechanical CAD, and software were pretty sharp. Physics analytics and lifecycle management were system concerns: Screening, decoupling, cooling outside the chip, making sure that thermal, ESD, EM, and aging fell within pre-agreed limits. Now boundaries are more diffuse with more complex application-specific SoCs and sensing in faster and more challenging processes, smaller enclosures complicating thermal management, tighter coupling between mechanical and electrical, stronger constraints on aging and operation in hostile environments, plus, of course, security and safety.

Tighter coupling leads to more interdependence in the design of the whole system. Failing to meet a requirement can have broader consequences, triggering a respin in silicon, multi-die systems, enclosures, mechanical design, or in software. Active lifecycle management is becoming more important for remote devices, in predictive maintenance applications, or where safety critical automation in automotive and aerospace applications must be checked frequently and should fail gracefully if a problem is detected.

Digital twins

Everyone endorsed digital twins to characterize and refine the complete system model before committing to manufacturing, seeing this as a better way to co-optimize each of these domains with quick turnaround and at much lower cost than doing the real thing. What a twin will look like depends very much on the domain. A twin for an assembly line or a jet fighter will necessarily have significant emphasis on mechanical content, supported by electronic enhancements. A twin for a data center or a fixed wireless access network would be more electronics-forward, with some mechanical support (cooling, for example).

Curiously, automotive is still figuring out which side of this divide it wants to be on. According to Alberto Sangiovanni-Vincentelli, who gave an earlier keynote, Tesla takes the view that they are fundamentally an electrical engineering and software engineering company. They start in electronic system architecture and then weave in the rest of the system, mechanical, etc., iterating to deliver the highest performance they can. In contrast, a traditional automotive OEM starts where they have always started—volume manufacturing and mechanical engineering. But, when they assemble electronics into the chassis, they blow their power envelope —at least compared to Tesla. This question of system design with electronics-forward or mechanical-/manufacturing-forward may be important not only here but in all systems where electronic content is rising rapidly.

Partnerships and coopetition

Clearly each of the panelists’ organizations have their own core strengths yet tread on each other’s turf in one way or another: Multiphysics, CFD, PLM, digital twins, 3D modeling, etc. This isn’t so unusual, especially in mechanical and industrial software. Customers want best in class solutions, as always. Vendors respond preferentially through organic growth or acquisitions (ex., the Siemens acquisition of Mentor Graphics). Siemens has their own MCAD and PLM offerings; Dassault and PTC are also established in those domains but do not have EDA capability or certain multiphysics options in-house so must rely on partnerships. However, none of them can cover all the bases. Even Siemens EDA (Mentor) must be augmented in several areas.

Conversely Cadence, which was historically concerned primarily with semiconductor design, now offers tightly integrated capabilities analytics and design capabilities around package and board assembly to ensure comprehensive solutions for design, electromagnetics, power distribution, EM, thermal and cooling. The Cadence focus on computational software drives in-house capabilities like CFD and datacenter energy optimization and, in a different direction, molecular simulation. Ansys, on the other hand, is squarely focused on what they call pervasive insights through multiphysics analysis as a capability you can call from anywhere, not only in the electronics domain.

All agreed that partnerships are essential to meet customer expectations, and that those partnerships consume a lot of energy. They must draw clear boundaries on where they compete and where they cooperate. Interestingly, difficulties are mostly in field and distributor organizations where alignment demands much more up-front and ongoing effort. At the technical level, multiple methods were suggested to simplify handshaking between tools.

Ansys has released a Python-compatible open-source version of all their APIs to GitHub. Linking clouds is another popular approach, particularly because speakers felt it easier to standardize and maintain interfaces in a cloud environment (where I assume versions and features are more easily controlled) than in on-premises platforms. Collaboration still depends on either standardized or de-facto standard interfaces; no one saw value in “universal” standards across such a diverse range of design domains.

One last thought here. Simulation Process and Data Management (SPDM) came up a few times in this discussion with regard to tracing digital threads across all simulation domains: Requirements, digital twins, test, model-based system engineering (MBSE) and verification management. I can’t find anything on the subject in core EDA; however, I do see Ansys and others making noise on the value of SPDM in complex system design. It will be interesting to see if this topic starts to appear in EDA also!

Very enlightening discussion on a topic of growing importance.

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Keysight EDA visit at #60DAC

Keysight EDA visit at #60DAC
by Daniel Payne on 07-24-2023 at 10:00 am
Categories: EDA, Keysight EDA

Keysight EDA 60DAC min

The opening day at DAC was Monday and I had an appointment with Simon Rance (Cliosoft) and Stephen Slater, Product Manager of Keysight EDA in their suite.  Back in February Daniel Nenni wrote about Keysight EDA acquiring Cliosoft, adding design data and IP management to their software offerings. I really wanted to hear how that acquisition was going at DAC.

Keysight EDA at DAC

Simon said that the Cliosoft product names would be changing from SOS to Keysight Design Data Management, and from HUB to Keysight IP Management. The Cliosoft president, Srinath Anantharaman was also at DAC, and he’s now the General Manager of the Design Data and IP Management group. The expanded scope for the Cliosoft products is now from specification to signoff, including simulation, test and manufacturing, really a full Keysight flow.  Simon was adamant interoperability with partner EDA flows is a critical element of the Design Data and IP Management solutions, and will continue to be in the future.

The other big trend for Keysight EDA is the use of HPC and cloud computing to speed up simulations in parallel, reducing run times from 24 hours down to 1-2 hours, boosting productivity, allowing more time for exploration and design trade-offs. Engineers use Keysight Design Cloud for speeding up both circuit simulations and EM simulation. These parallel simulations can be executed through an on-premise cluster or a private, public or a hybrid cloud. So lots of choices to get faster simulation results.

Yes, the Design Data and IP management tools will continue to be supported alongside of other EDA vendor environments: Cadence, Siemens, Synopsys, Ansys, Altium, Zuken, MathWorks, Silvaco, Empyrean.

Keysight EDA Partners

Also announced at DAC this year was a Python API framework so that EDA tools can have inter-tool workflows for IC/Package/Board designs that have RF, uWave and high-speed digital requirements. With the new Python workflow, engineers can create custom workflows to automate sequential tasks, move data more easily between tools, turn data into an executable model, and even bring Test & Measurement into the design process.

Keysight EDA – Python workflow

The Cliosoft tools are all integrated into the PathWave Design 2024 software suite, and that was completed in record time since the acquisition.

Summary

All of the Cliosoft people that I saw at DAC were quite happy with being part of Keysight EDA, and the booth traffic was high. There was a good buzz in the booth, and the suites were filled with customer meetings, so the future looks promising. Learn more about their EDA tools, Data and IP Management, and the Design Cloud online.

Related Blogs

 

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NILS Enhancement with Higher Transmission Phase-Shift Masks

NILS Enhancement with Higher Transmission Phase-Shift Masks
by Fred Chen on 07-24-2023 at 8:00 am
Categories: Lithography
2 Comments

Figure 1. NILS is improved

In the assessment of wafer lithography processes, normalized image log-slope (NILS) gives the % change in width for a given % change in dose [1,2]. A nominal NILS value of 2 indicates 10% change in linewidth for 10% change in dose; the % change in linewidth is inversely proportional to the NILS. In a previous article [2], it was shown that NILS is better for a dark feature against a bright background than the other way around. Attenuated phase shift masks (attPSMs) help to improve the NILS to reach values of 2 or more, in cases where conventional binary masks can’t without an exorbitantly high dose.

Increasing the transmission of the attenuated phase shift mask [3] takes the improvement further. A higher transmission effectively makes the dark areas darker, which increases the image log-slope.

Figure 1. NILS is improved for higher transmission of the attenuated phase-shift mask. The images are taken along the long axis of a dense oblong (1.3:1) pattern with cross-dipole illumination. The graph on the right uses the log scale instead of linear scale for the y-axis, representing intensity. The more obvious dip indicates better NILS for the higher transmission (16% vs 6%).

Besides improving NILS, the mask error sensitivity and depth of focus are also improved [3]. Improving the NILS is particularly important for improving the resolution of 2D shapes such as in Figure 1 or in the header above this article. For the 12% attPSM of Ref. 3, a square feature width of 65% of pitch with cross-dipole illumination (for tightest 2D resolution: dipole illumination in X + dipole illumination in Y) just manages to hit a NILS of 2.0 in both x and y. This is another opportunity to improve 2D resolution for DUV, especially for core patterning for self-aligned double patterning (SADP) [4].

References

[1] C. A. Mack, “Using the Normalized Image Log-Slope,” The Lithography Expert, Microlithography World, Winter 2001: http://lithoguru.com/scientist/litho_tutor/TUTOR32%20(Winter%2002).pdf

[2] F. Chen, “Phase-Shifting Masks for NILS Improvement – A Handicap for EUV?”, https://www.linkedin.com/pulse/phase-shifting-masks-nils-improvement-handicap-euv-frederick-chen

[3] T. Faure et al., “Development of a new high transmission phase shift mask technology for 10 nm logic node,” Proc. SPIE 9984, 998402 (2016).

[4] H. Yaegashi et al., “Overview: continuous evolution on double-patterning process,” Proc. SPIE 8325, 83250B (2012).

This article first appeared in LinkedIn Pulse: NILS Enhancement with Higher Transmission Phase-Shift Masks

Also Read:

Assessing EUV Wafer Output: 2019-2022

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

A Primer on EUV Lithography

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Intel Enables the Multi-Die Revolution with Packaging Innovation

Intel Enables the Multi-Die Revolution with Packaging Innovation
by Mike Gianfagna on 07-24-2023 at 6:00 am
Categories: Foundries, Intel Foundry
2 Comments

Intel Enables the Multi Die Revolution with Packaging Innovation

The trend is undeniable. Highly integrated monolithic chips can no longer handle the demands of next-generation systems. The reasons for this significant shift in design are many. Much has been written on the topic; you can get a good overview of the forces at play in multi-die design here. These changes represent the next chapter in the pursuit of exponential scaling originally defined by Moore’s Law. So, it is quite natural to look to Intel, the birthplace of Moore’s Law, for a peek at what lies ahead. Read on to see how Intel enables the multi-die revolution with packaging innovation.

The Packaging Challenge

The move to multi-die systems creates substantial design and manufacturing challenges. Billions of transistors are now spread across multiple dies integrated with complex package form factors containing millions of bump connections. The resultant heterogeneous integration demands a silicon, package and board co-design approach. 

Conventional approaches to these challenges often involve a silicon interposer to implement a “2.5D” integration. Drawbacks of this approach include the cost of the extra silicon and increased design complexity and reduced yield. The number and type of dies that can be integrated is also limited with this approach.

Finding a Better Way – EMIB

Intel has found a way around many of the current limitations of 2.5D packaging. Embedding a small silicon bridge chip into the package is the answer. EMIB, or embedded multi-die interconnect bridge, delivers a cost-effective way to connect multiple dies within a package. An overview of the approach is provided in the figure below.

EMIB Overview

A highly scalable capability is delivered with EMIB. There is now flexibility in total design size, number of chiplets bridge dimensions, and localized optimizations to support a wide variety of heterogeneous configurations. EMIB has been proven on several designs, as shown in the figure below.

Real Product Examples

Implementing EMIB – The Power of the Ecosystem

EMIB-based package design has its own set of challenges. The approach presents high pin count, net count and design density. An example design could contain 24 layers, 52,000 nets and 240,000 pins. All this must be managed across a heterogeneous design flow to achieve low latency and optimal energy efficiency.

Intel Foundry Services (IFS) have repeatedly stated their commitment to bring Intel technology to customers via the industry standard and powerful avenue of a foundry ecosystem. Staying true to that commitment, Intel approached this problem with standards and ecosystem collaboration. Data management, silicon/package/board co-design, consistent modeling/analysis and optimized cost and performance via design reuse are all supported with a comprehensive package assembly design kit (PADK). The PADK contains:

  • EMIB Design Guide
    • SI/PI Collateral
    • Thermal Tolerance
    • Mechanical Parameters
  • Package Library
    • Layout Template
    • Padstacks/Pins/Vias
    • Parts and Fiducials
  • Stack Up
    • Thickness
    • Tolerance
  • Design Rule Specs
    • Manufacturing Checks
    • Assembly Checks
    • Design Rule Checks
  • Performance
    • Electrical Rules
    • Constraints

Using this information, Intel built an EMIB-based reference flow with its key EDA partners. There is a design and an analysis reference flow in development. The figure below summarizes the status of each flow across the ecosystem.

Design Flow Status

What’s Next

There is much more to come from Intel in this area. Additional work includes:

  • Die-to-Die IP with UCIe
    • Reusability, compatibility, standardization
  • EDA-CAD agnostic standards
    • Chiplets, tech files, collateral, kits with end-to-end focus for ecosystem development
  • EDA framework
    • Silicon/package/system co-design
    • Interoperable EDA tools, flows and methods
    • Data exchange and workflows

The Intel view is that advanced packaging technology, content density, and package complexity requires new methods to drive design efficiency. The focus is to collaborate for ecosystem development using design standards and vendor agnostic tools, flows and methods.  And that’s how Intel enables the multi-die revolution with packaging innovation, and IFS delivers it to the external customers.

Also Read:

Intel Internal Foundry Model Webinar

VLSI Symposium – Intel PowerVia Technology

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Podcast EP173: The Impact of Celestial AI’s Photonic Fabric on the Future of High-Performance Architectures

Podcast EP173: The Impact of Celestial AI’s Photonic Fabric on the Future of High-Performance Architectures
by Daniel Nenni on 07-21-2023 at 10:00 am

Dan is joined by Dave Lazovsky, CEO of Celestial AI. Dave has an in-depth knowledge of semiconductor, data/telecommunications, photonics and clean energy industries, as well as extensive international business experience. He currently has over 50 issued and 5 pending U.S. patents.

In this broad and forward-looking discussion, Dave explains the incredible demands being placed on next-generation compute architectures. He explores the capabilities of Celestial AI’s optical interconnect technology platform for memory and computation. He describes the game-changing impact the company’s Photonic Fabric can have on performance, energy efficiency and flexibility.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover

ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover
by Robert Maire on 07-21-2023 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

ASML 2023 Results

-ASML reports better results & guide despite China restrictions
-Supports our view of China issues not that impactful longer term
-Industry recovery seems very far off with more delays
-ASML remains the best, most robust story in a weak industry

ASML reports nice beat despite China concerns

ASML reported revenues of Euro6.9B of which Euro5.6B was for systems with EPS of Euro4.93 . This is roughly $7.52B in revenues and $5.37 in EPS versus street estimates of $7.48B and $5.10…so a nice beat.

Guidance is for between Euro6.5B and 7.0B in revenues. At the midpoint this is roughly $7.57B versus expectations of $7.14B.

Margins remained above 50%.

Perhaps most importantly, ASML expects that growth in 2023 will be roughly 30% above that of 2022 which is up from prior expectations of 25-27%.

All in all a very good quarter despite industry weak conditions and macroeconomic uncertainty.

Confirms our view that China impact is minimal and not significant

We have suggested since the start of sanctions on the sale of litho tools to China that the overwhelming demand for ASML’s tools would more than offset tools impacted by sanctions. This appears to be the case as demand from China for older technology tools is stronger than ever.

We think investor concerns continue to be overblown as overall demand remains quite strong despite the prolonged industry downturn.

Semiconductors remains a zero sum game

In the long term, semiconductor production will remain a zero sum game. By that we mean that chips not produced in China will have to be produced elsewhere by some other country perhaps at a slightly higher cost but using the same ASML tools that China would have otherwise bought.

In a way, the restrictions on sales to China may help to diversify demand and chip production across the globe so that China does not dominate both the purchase of tools as well as production.

While this may cause disruption in the near term it likely is better for all in the long term as it prevents the total domination we have seen from China in both the solar and LED markets. We wouldn’t want what happened in those markets to happen in the much more critical chip market.

We strongly maintain our belief in the control of exports of chip equipment to China to prevent that from happening for both defense and economic concerns.

China is buying plenty of DUV tools anyway

Its certainly not like China isn’t buying a lot of tools from ASML as they can still buy DUV tools and continue to do so in large quantity. The DUV business for ASML remains quite robust at almost 50% of overall business. Up from prior quarters.

Memory even worse than before, almost down by 50% Q/Q

While logic and foundry, especially in trailing edge remains strong, memory continues its nosedive with memory related sales dropping by almost half quarter over quarter from 30% of sales in Q1 to just 16% of sales in the just reported quarter.

As we have continued to repeat…memory is very, very ugly. There is no recovery in sight and capex continues to trend down in memory to just sustenance levels and no more

Fab delays are impactful

We had mentioned in our note from SEMICON West last week that we were growing concerned about delays in planned fab construction and likely further delays and cancelations as capacity is clearly not needed in foundry/logic and especially not in memory which is swimming in capacity.

ASML pointed out that fab utilization remains low which means tool utilization is low. ASML said that fab delays are delaying and pushing out deliveries of equipment.

We clearly haven’t seen the end of this and fab delays will likely worsen as the downturn extends into next year.

Right now we are just seeing delays but some of that could turn to cancelations if the fabs they were intended for get canceled.

Fantastic job on DUV offsets weakness to some extent

ASML is now talking about shipping a staggering 375 DUV tools of which 25% would be immersion. Rather than Euro3B of revenue that was expected to be delayed from 2023 to 2024, ASML has instituted some fast ship protocols and will see an additional Euro700M in 2023.

This helps offset other weakness and contributed to increasing the overall 2023 growth rate.

This obviously helps make up for slowing EUV sales which were expected to grow 40% Y/Y but now expected to grow only 25% Y/Y.

The book to bill wasn’t great with Euro4.5B in orders but the backlog remains strong and long at Euro38B, a huge number that will continue to keep ASML warm through the now lengthened chip winter.

Somewhat worse news on industry downturn confirms our pessimistic view

We have been suggesting since the beginning of this downcycle almost a year ago that this down cycle would be worse than most due to a variety of circumstances. This appears to be the case and the prolonged downturn seems to have been communicated in ASMLs report as they had essentially no hint of a recovery and a number of factors worsened.

We have also clearly communicated that we can’t have a significant recovery of the overall industry without memory recovering as well….it just doesn’t happen that way.

Right now memory is as bad as ever. Pricing remains low, bloated inventories, lowered production, cut capex…..all bad signs on top of macro economic issues.

AI is not the savior of AI and we think investors may be figuring that out

The stock- A beautiful mansion with a moat in an ugly neighborhood

If we had to buy one semiconductor equipment stock ASML would be it. Growing 30% Y/Y during a downturn is just amazing. They are a true monopoly with dominant market share and technology with zero competition.

China issues are not impactful in our view and could offer long term benefit.

The long term semiconductor view remains very positive.

The obvious problem is that in the near term the industry remains ugly. ASML will outperform the group by far during the downturn as they are already proving. They will also be the first out of the downturn as litho tools are the first thing you buy for your new fab.

We would equate ASML to being a beautiful, well built mansion with a deep moat around it in a neighborhood that is going through a difficult period of transition.

It may be the best home in town but investors may be concerned about buying in at this particular point in time given the overall neighborhood condition, thus we will see a weak stock despite financial & technical out performance.

We view this report more negatively for others in the semiconductor equipment space as it suggests a longer downturn that we have predicted and as we mentioned last week, investors may start to get impatient as the recovery seems further away tahn hoped.

Also Read:

SEMICON West 2023 Summary – No recovery in sight – Next Year?

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory

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Upskill Your Smart Soldiers and Conquer the Chip War in Style!

Upskill Your Smart Soldiers and Conquer the Chip War in Style!
by Sivakumar PR on 07-21-2023 at 6:00 am
Categories: Maven Silicon, RISC-V, Semiconductor Services

Maven Silicon Article Figure 1

My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform our industry into a trillion-dollar industry with their inventions and innovations. So, in this article, I want to explain how Maven Silicon can collaborate with your organization as the VLSI Centre Of Excellence for upskilling your chip design workforce and why you should choose Maven Silicon as your preferred VLSI training partner.

To understand ‘Why Maven Silicon for upskilling your workforce?’ – Let me convince you with our USPs.

Maven Silicon USPs:
  1. Scalable Training Services: Maven Silicon is the only VLSI training company that can train engineers in bulk worldwide using our cloud-based online training solutions. We are the one who introduced this kind of innovative learning subscription model to tier-1 global product and services semiconductor MNCs. Today we train thousands of VLSI engineers every year for our enterprise customers. At Maven Silicon, we also provide ILT-Offline and VILT-Blended-online courses for project-specific specialized training courses. So, we can support your workforce L&D initiatives at any scale as per your business requirements.
  2. Flexible Business Models: We offer inexpensive multi-year learning subscription business models to upskill an army of engineers globally, along with our standard corporate training business models, which involve training a batch of engineers [Instructor-Led Offline Project/Domain specific Specialized Training] periodically for various projects.
  3. Domain Expertise: Maven Silicon has been designated as ARM Approved Training Partner by ARM and Global RISC-V Training Partner by RISC-V International to train the VLSI engineers on their processor architectures. Synopsys and Siemens EDA are our EDA partners. All our lead trainers have been trained formally by our industry partners ARM, RISC-V, Synopsys, and Siemens EDA. Our trainers are specialized in various VLSI domains like RTL Design and Verification, DFT, Physical Design, SoC Design, ASIC & FPGA, ARM and RISC-V. The image below explains how we offer various VLSI courses and support our enterprise customers with our domain expertise and flexible business models.

Click here to view the full image

I also want to share some of the myths and fallacies about upskilling the VLSI engineers we observed while interacting with the project managers and business heads in India and explain how we can collaborate with your L&D team to address their challenges or concerns.

Myths & Fallacies:

1) Internal Training is very effective and inexpensive: Internal training might be effective, but it’s not a scalable model. Refer to our USPs 1&2. Involving your experienced and expensive project managers as trainers in the internal training programs will be more expensive than involving external vendors. Training services are our core business, so we deliver our courses efficiently with our unique pedagogy and curricula. We regularly learn new technologies and update our curricula.

A traditional, highly experienced project manager may not be competent to train the next generation of engineers on the latest technologies and design methodologies. For example, V-Plan based CRCDV using UVM is different from Test plan-based HDL verification. Some experienced traditional DV project managers refer to the Test plan [Directed testcases] while using UVM/SystemVerilog, like how we casually use the term ‘DUT’ for DUV. Can they quickly unlearn traditional and outdated techniques/methodologies? What if they leave your company because of this additional training responsibility – teaching, developing, and maintaining course content? What about the additional efforts and expenses incurred by your LMS software and EDA licenses? What is your core business – EDA or Product or Design Services, and why don’t you dedicate your expensive, experienced resources to grow your core business?

2) External Training is expensive: Why should a billion-dollar VLSI company be conservative as miserliness for upskilling its workforce? It’s time for us to think beyond free learning subscriptions and internal training programs and invest more in new L&D initiatives to support our VLSI engineers for their long-term career development. Refer to our USPs 1&2. We offer various online and offline VLSI training programs with flexible business models to upskill your engineers efficiently within your L&D budget. Companies that support engineers generously for their long-term career growth can retain them for long and grow them as next-generation leaders. Hiring culturally fit experienced engineers, project leads, managers, architects, and engineering directors from competitors is very expensive than investing in L&D upskilling initiatives. Isn’t it?

3) Internship is more effective than direct hiring: Whether direct hiring or internship, it can be more effective only with proper training and coaching/mentorship. In the case of hiring New College Graduates, we partner with our customers to upskill them using our pre-onboarding NCG training courses. It is unique as this pre-onboarding training begins during their engineering course during the pre-final/final year. It works beautifully for the companies to onboard them efficiently without much attrition. Most electronics/electrical engineers are still attracted to the software giants because of the lucrative career and complexity of the VLSI technology. Formally upskilling passionate engineers can help them to deal with VLSI comfortably. So, they will choose our industry and pursue their long-term VLSI career. The internship is more effective with our pre-onboarding training, and it reduces the duration and cost of the internship minimum of 50% for the company. Why do you still want to follow the same informal/traditional on-the-project internship/training? Is it effective?

We can dream about transforming our semiconductor industry into a trillion-dollar industry only with creative and skilled chip design engineers. We need next-gen advanced node chips to implement and support new technologies like AI, 5G, Cloud, etc., and grow our business. We need more creative and skilled engineers for the same. Are we gearing up with the next generation of skilled chip designers to design more new chips, especially working chips, and make the fabs busy?

Also Read:

Chip War without Soldiers

Maven Silicon’s RISC-V Processor IP Verification Flow

Is your career at RISK without RISC-V?

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The Efabless Generative AI Challenges and Why They Matter

The Efabless Generative AI Challenges and Why They Matter
by Daniel Nenni on 07-20-2023 at 10:00 am
Categories: Efabless, Semiconductor Services

Efabless Banner for SemiWiki

Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series.  As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create Verilog and implemented their designs using the Efabless chipIgnite platform and its OpenLane open-source design flow. The first-place winner was a co-processor by Hammond Pearce at New York University; you can read the story here.  Silicon for the winners will be fabricated by Efabless and the devices are expected back at the end of October.  The second challenge has the same guidelines but the time to design is extended from three weeks to two months.

There is obviously lots of interest in Generative AI in chip design.  It promises to speed and simplify the design of chips, making custom silicon economically feasible across a previously unimaginable diversity of designs to meet the breadth of requirements for IoT and Machine Learning.  That being said, there are still lots of questions.  Are the data sets large enough to enable the LLM models required?  How will verification be done to the appropriate levels of completeness?  How will people learn and adapt to this new approach?  Will the chips work?  Will people actually trust that they do work?

Efabless plans to address these concerns and accelerate the emergence of the new world.  They      believe that the key is to engage the maximum number of potential users to drive the maximum number of designs, enable collaboration and sharing of experiences and designs and, last but far from least, to provide a full path to manufacturing because “the proof is always in the pudding.”  The answer lies in open source and community models, an approach that Efabless has proven over the past several years.

Here is how:

Open Source is fundamental.  By putting prompts and designs in the public domain they can be studied by others and used as starting points for future designs.  In short order a vast array of examples will be created to expand the potential data sets.  The use of the open source design flows and the automation offered by Efabless expands the number of potential designers (and therefore the number of designs) by lowering barriers to entry.

Community engagement adds to the success.  It was remarkable how contestants openly collaborated in the first challenge, sharing their learnings in both design and verification.  As the number of contestants grows it stands to reason that the collective insights will grow exponentially with it.

Prototyping is key. Last but not least, Efabless has addressed the last mile to manufacturing, making it both fast and affordable at scale.  This enables attractive incentives for people to participate in the journey and very importantly it rapidly closes the loop to show which prompts, methods and, ultimately, AI generated designs are most effective.

Mike Wishart, CEO, has described the very logical fit of generative AI with Efabless and its mission to simplify design and open it to everyone.  It now seems that Efabless will be a key enabler in accelerating its adoption.

Also Read:

Efabless Celebrates AI Design Challenge Winners!

Why Generative AI for Chip Design is a Game Changer

A User View of Efabless Platform: Interview with Matt Venn

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Reducing Electronic Systems Design Complexity with AI

Reducing Electronic Systems Design Complexity with AI
by Kalar Rajendiran on 07-20-2023 at 6:00 am
Categories: AI, EDA, Siemens EDA

Siemens Reducing Complexity with AI Whitepaper Graphics

 

In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, and potential design flaws. Siemens EDA recognizes the urgent need for innovative solutions to overcome these obstacles. The company has identified artificial intelligence (AI) as a technology that could offer tremendous leverage for innovation. AI encompasses computational technologies that enable machines to reason and infer without human intervention. AI solutions can analyze large volumes of data to identify patterns and trends, improving processes and providing recommendations for better decision-making.

Siemens EDA has been making significant investments in AI technologies and applying them to various product areas, including PCB design, autonomous driving systems, smart factory floor management and smart city management. The company recently published a whitepaper that delves into how the application of AI technology can address the challenges in printed circuit board (PCB) design.

Challenges in PCB Design

PCB electronic systems engineers face challenges in designing complex, fast ICs that require adequate power, cooling, signal integrity, and thermal integrity. They must deliver high-performance PCBs and interconnected electronic systems within shrinking time-to-market windows while minimizing power consumption. Understanding PCB design and EDA tools involves a steep learning curve and engineers often learn on the job. Component selection is another challenge that requires extensive research and analysis of datasheets.

Leveraging AI

AI can mine completed designs to identify patterns and guide designers to the next logical step, improving design quality and efficiency. AI can develop models based on historical information to recommend viable component options, speeding up the selection process. Integrate this with real-time visibility into component supply chain and it turns into a powerful capability.

The ultimate goal of AI-driven electronic design is for AI algorithms to generate PCB designs and manufacturing outputs, reducing design time and eliminating costly mistakes.

Generative Design

Generative design is an innovative approach that uses algorithms and computational methods to automatically generate and optimize design solutions based on specified parameters and constraints. It combines the power of artificial intelligence, machine learning (ML), deep learning (DL) and advanced simulation techniques to explore a vast design space and produce optimized and efficient designs.

Benefits of Leveraging AI in Electronic Systems Design

Generating component models, such as symbols, physical geometries, and simulation models, is time-consuming. AI technologies like natural language processing and image recognition can automatically process datasheets and generate the required models, reducing manual effort and leveraging domain knowledge.

Schematic connectivity, establishing connections between components, is another manual task. ML models trained on completed designs can recommend components and suggest pin-to-pin connections, accelerating the design process.

Dynamic reuse of functional blocks and intelligent database management can be achieved by training DL models, enabling design tools to predict potential functions of blocks and suggest reusable placement and routing options.

Constraints, such as layout, high-speed design, manufacturing, and test rules, are usually entered manually, posing a risk of errors. AI can recommend constraint sets and values based on the current design and knowledge from released designs, streamlining the process.

Layout tasks like component placement and routing are time-consuming. AI systems can recommend placement and routing strategies based on completed designs, and advanced routing methodologies like sketch routing can be applied. Auto routing and analysis tools can also benefit from AI/ML algorithms to generate optimal routes and perform accurate simulations.

Summary

AI is increasingly important in enhancing operational productivity and user expertise. In PCB design, AI is particularly valuable in automating manual processes and enabling entry-level users to perform tasks that previously required expert knowledge. By leveraging AI technologies, decision-making can be accelerated, mundane processes can be automated, new users can work more efficiently, and the performance and manufacturability of multi-domain systems can be optimized.

As part of the Siemens Xcelerator portfolio, AI-driven tools enable electronic systems design companies to leverage AI technologies and bring futuristic products to market. Siemens continually identifies new use cases where AI can be applied to improve design tools and invests time and resources in enhancing existing algorithms or developing innovative methodologies to address challenges.

This whitepaper is a valuable read for everyone involved in the electronic systems design process.