DAC2025 SemiWiki 800x100
Semiconductor Expert Forum

Posted on

2022 Retrospective. Innovation in Verification

2022 Retrospective. Innovation in Verification
by Bernard Murphy on 01-18-2023 at 10:00 am
Categories: AI, Cadence, EDA

Innovation New

As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. And don’t forget to come see us at DVCon, first panel in the morning on March 1st 2023 in San Jose. Bring your own favorite ideas to share with us!

The 2022 Picks

These are the blogs sorted by popularity. We averaged a little over 10K hits per blog, an encouraging sign that you continue to enjoy this series. As usual the hottest blog was the retrospective, very closely followed by hazard detection using Petri Nets. The latter scored significantly above the average, suggesting we should invest more time in this topic through the coming year. Memory consistency checking, advances in coverage and security also ranked high. We’ll follow your interests by reviewing more papers on these topics through 2023.

2021 Retrospective. Innovation in Verification

Hazard Detection Using Petri Nets. Innovation in Verification

Post-Silicon Consistency Checking. Innovation in Verification

Dynamic Coherence Verification. Innovation in Verification

ML-Based Coverage Refinement. Innovation in Verification

Symbolic Trojan Detection. Innovation in Verification

Refined Fault Localization through Learning. Innovation in Verification

Validating NoC Security. Innovation in Verification

Ant Colony Optimization. Innovation in Verification

Formal at System (July)  Level. Innovation in Verification

Test Ordering for Agile. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification

Paul’s view

A third year of blogging on innovation in verification, and I’m still really enjoying it. I truly believe verification is essentially the infinite problem: if you double the gate count you square the state space, and verification is a problem of covering the state space. There is no such thing as being “done”, there are always more devious bugs to be found if time and budget permit. I am grateful to all those of you in academia and industry who continue to research, innovate, and publish your works. The need and opportunity is definitely there!

Looking back on 2022 it was a year of blogging about cool algorithms. I learned about using Ant Colony Optimization in model checking (link). I read two papers that used genetic programming to improve test quality – one on increasing coverage of cross-domain FIFO stalls in big GPUs (link) and another on biasing random instruction generators to produce more memory race conditions (link).

Then there were three papers leveraging neural networks to improve productivity – to predict test failures and test coverage (link), to automatically root cause bugs (link), and to prioritize which tests to run and in what priority order (link).

We also blogged about a neat formal method for abstracting a design to the system level using temporal logic assertions (link), and I had a wonderful walk down memory lane back to my PhD days with a paper on using Petri nets to detect hazards in asynchronous interconnect (link).

Lastly, we zoomed in on a few papers applying formal methods to security verification – on one Trojan logic detection (link) and the other on NOC security (link).

Stepping back from our blog and looking to our industry at large, AI-driven verification and system level verification continue to stand out as big trends. 8 of the 11 papers we covered last year fall under these two big buckets. Here’s looking forward to another fun year of blogging on some more innovations in verification!

Raúl’s view

This is my second year with the Verification Blog and, if nothing else, I have learned a lot (and I hope so did you!) In 2021 the main themes (which of course overlap) we encountered in our random walk included higher levels of abstraction (power side channel leakage, memory consistency at the RTL, Instruction-Level) as well as specific verification aspects such as how to detect flipped Flops and Concolic Testing. We also covered papers on ML/NN (obligatory).

These themes continued to be prevalent in 2022. In the realm of higher levels of abstraction, we explored hazard detection using Petri nets (August, the most popular post, I wonder if the interest was sparked by Petri Nets or hazards/synchronous systems?), the equivalence of higher-level abstraction and RTL (July), and formal properties for NOC security (December). We also looked at how machine learning is being applied to a wide range of verification challenges, including covering hard-to-reach branches (April), fault localization in software (May), and test case selection and prioritization for agile software development (September). Other notable topics we covered included IBM’s Threadmill for post-silicon testing (October), memory consistency verification using genetic algorithms (February), Trojan detection (March), model checking with ant colony optimization (November), and FIFO stall verification (June).

In addition to technical merit and marketability, we also began considering citations and follow-up work. While our sample of two dozen papers is by no means exhaustive, our goal is to give readers a sense of the diverse range of approaches used in verification. And, let’s be honest, where else can you learn about stalling FIFOs, delve into Petri nets, and discover that ants are more effective when they carry food pheromones?

Posted on

IEDM 2022 – Imec 4 Track Cell

IEDM 2022 – Imec 4 Track Cell
by Scotten Jones on 01-18-2023 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
11 Comments

2022 IEDM Presentation Session23 2 VictorVega Page 03

At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.

Logic designs are built up by standard cells such as inverters, NAND gates, scanned flip-flips and other cells. The width of a standard cell is some number of contacted poly pitches (CPP) depending on the cell type and whether the cell has a single or double diffusion break, for example a 2-input NAND gate will be 3CPP wide for single diffusion break and 4CPP wide for double diffusion break. The height of a standard cell is characterized by the metal 2 pitch (M2P) multiplied by the tracks (number of M2P).

As it has become increasingly difficult to scale CPP and M2P, design technology co-optimization (DTCO) has become increasingly important in scaling with techniques such as reducing the tracks. Currently minimum cells are generally 6-tracks with some 5-track cells emerging. In this paper Imec discusses routing techniques to enable a 4-track cell.

Figure 1. presents the Imec roadmap from 9-tracks down to 4-tracks.

Figure 1. Imec scaling roadmap.

Before getting into the routing techniques described here, I wanted to touch briefly on other requirements for cell height scaling, simply talking about M2P and tracks ignores the underlying device structure. The cell height must fit the n and p FETs, n-to-p spacing and boundary widths. The transition from FinFETs to Horizontal Nano Sheets (HNS) provides scaling of the n and p FETs by switching from multiple fins taking up horizontal space to a stack of nano sheets in the vertical direction. Techniques such as forksheets (FS) and buried power rails (BPR) are additional options Imec is developing to address the device height, for example BPR can replace wide metal-2 power rails with tall-thin power rials in the substrate reducing boundary widths, and forksheets can reduce n-to-p spacing. Irrespective of the particular techniques employed the devices must be interconnected.

Leading edge processes have seen the introduction of middle-of-line interconnect layers under the metal-1 layer, these additional layers are typically referred to as Metal 0 (M0) or Mint in Imec’s terminology. To get to a 4-track cell a single M0 layer is not sufficient to interconnect the device. In this work an M0A and M0B are added underneath Mint and in a novel process architecture Mint is used as a mask to perform a tip-to-tip cut in M0B.

Mint connects down to M0B through a via VintB and down to the gate contact through VintG. M0B connects to source drains through Via V0A down to M0A.

Figure 2 illustrates the congestion in a 4-track cell with Mint and Figure 3 illustrates the addition of M0B and M0A.

Figure 2. Congested Cell with Mint only.

Figure 3. Congestion Fixed with addition of M0B and M0A.

To achieve the required tight tip-to-tip spacing a self-aligned cut is used for M0B where Mint acts as the mask, this requires a subtractive metallization process. The metallization utilized here is ruthenium (ruthenium can be dry etched unlike copper) deposited using the semi damascene technique, see figure 4.

Figure 4. Semi-Damascene.

The self-aligned M0B cut is illustrated in figure 5.

Figure 5. M0B Self-Aligned Cut.

By adding two layers and using a self-aligned cut and a 4-track cell can be interconnected. Provided the underlying device structure can also achieve the required scaling this interconnect scheme provides a path to 4-track cells and continued scaling.

 Also Read:

IEDM 2022 – TSMC 3nm

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

IEDM 2022 is shaping up

Posted on

Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning

Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning
by Fred Chen on 01-17-2023 at 10:00 am
Categories: Lithography
4 Comments

Application Specific Lithography 1

The pursuit of ever smaller DRAM cell sizes is still active and ongoing. DRAM cell size is projected to approach 0.0013 um2 for the D12 node. Patterning challenges are significant whether considering the use of DUV or EUV lithography. In particular, ASML reported that when center-to-center values reached 40 nm, single patterning would not be recommended even for EUV [1]. In this article, we will show that for the 12nm DRAM node and beyond, capacitor center-to-center is expected to go below 40 nm, therefore requiring multipatterning.

DRAM cell layout for Storage Capacitors

Storage capacitors are arranged in a hexagonal array (Figure 1). The active area design rule is determined by the bit line pitch and word line pitch [2].

Figure 1. Storage nodes (yellow) on a DRAM cell grid. BLP=bit line pitch, WLP=word line pitch.

A 38 nm bit line pitch and 33 nm word line pitch would lead to a center-to-center of 38 nm and a pitch of 32.9 nm between diagonals, for a cell size of 0.001254 um2 and just under 12 nm active area design rule.

For a 0.33 NA EUV system, the hexagonal array would use a hexapole illumination, where each pole produces a three-beam interference pattern (Figure 2). The four quadrant poles produce a different pattern than the other two horizontal poles. This leads to two separate dose components with separate stochastics. These are added in the final, composite pattern.

Figure 2. Hexapole illumination for DRAM storage pattern consists of 4 quadrant poles (grey) and two horizontal poles (yellow). Depending on the illumination direction, the resulting three-beam interference pattern has a specific orientation.

Due to substantial absorbed photon shot noise at the feature edge, the stochastic effect on pattern placement error is significant, as already disclosed in Ref. 1, easily exceeding a 1 nm overlay spec. The lower absorbed dose appears to be obviously worse (Figure 3).

Figure 3. Stochastic placement error (X only) of central pillar in 38 nm x 66 nm unit cell (word line pitch = 33 nm), with the expected hexapole illumination in a 0.33 NA EUV system. Here a series of 25 different instances is shown for two absorbed doses.

Going to 0.55 NA adds the issue of severely reduced depth of focus. An NA of 0.55 would result in a 15 nm defocus leading to >50-degree phase shift between the innermost and outermost diffraction orders (Figure 4), which severely reduces the image contrast due to fading [3].

Figure 4. 15 nm defocus on a 0.55 NA EUV system leads to a >50-degree phase shift between the innermost and outermost diffraction orders.

Thus, it is likely the storage node pattern needs to formed from two crossed line patterns (Figure 5). Each crossed line pattern can be formed by a EUV single exposure or by DUV SAQP (self-aligned quadruple patterning). Both options are single-mask processes. The SAQP process is more mature (having long preceded EUV) and free from the secondary electron stochastic concerns of EUV [4], so it should be preferred. Still, for the SAQP case, the spacer lines must be well-controlled both in terms of placement and linewidth roughness [5].

Figure 5. The storage node pattern can be formed by the intersection of two crossed line patterns.

Instead of line-type SAQP, a 2-D spacer honeycomb patterning was also demonstrated by Samsung [6], utilizing a single mask with a starting honeycomb pattern, instead of two masks with starting line patterns.

While the case above considered 38 nm bit line pitch and 33 nm word line pitch, it applies also to the case where the pitches are swapped (33 nm bit line pitch and 38 nm word line pitch), due to the hexagonal symmetry.

References

[1] W. Gao et al., Proc. SPIE 11323, 113231L (2020).

[2] F. Chen, Trigonometric Relationship Among DRAM Cell Pitches, https://www.youtube.com/watch?v=Oq6b-6iw6Zk

[3] J-H. Franke, T. A. Brunner, E. Hendrickx, J. Micro/Nanopattern. Mater. Metrol. 21, 030501 (2022).

[4] F. Chen, Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects, https://www.linkedin.com/pulse/secondary-electron-blur-randomness-origin-euv-stochastic-chen/

[5] N. Bae et al., Proc. SPIE 11615, 116150B (2021).

[6] J. M. Park et al., IEDM 2015.

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning

Also Read:

Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects

Predicting EUV Stochastic Defect Density

Electron Blur Impact in EUV Resist Films from Interface Reflection

Posted on

Alphawave IP is now Alphawave Semi for a very good reason!

Alphawave IP is now Alphawave Semi for a very good reason!
by Daniel Nenni on 01-17-2023 at 6:00 am
Categories: 5G, Alphawave Semi, IP
1 Comment

datacenter technology sq

The semiconductor ecosystem has been full of interesting twists of late and Alphawave has been a company to watch since the very beginning. Alphawave came out of stealth mode in early 2019 as the world’s first IP company focused on multi-standard connectivity (SerDes) IP solutions. The importance of SerDes had been understated prior to Alphawave (my opinion) but clearly that is no longer the case. The recent twist is the company’s name change which most of us saw coming after the OpenFive acquisition:

“Announced a new brand, Alphawave Semi, which reflects our ambition to build the leading vertically integrated semiconductor company focused on connectivity solutions. Our new identity preserves the Alphawave brand that our customers have come to depend upon and trust. With Alphawave Semi we expand our capabilities to service our customers – with a portfolio of connectivity IP, custom silicon, and connectivity products.”

This name change is important but let’s start from the beginning. Alphawave’s founders had previously worked together for many years across several different companies:

Tony Pialis co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. Prior to Alphawave, Tony cofounded Snowbush Microelectronics which is currently part of Rambus and V Semiconductor which is part of Intel.

Jonathan Rogers co-founded Alphawave in 2017 and has since served as its Senior Vice President of Engineering. He was Director of Design Engineering at V Semiconductor and Gennum. He was also the Director of IP Development and IC Designer at Snowbush Microelectronics Inc.

Raj Mahadevan co-founded Alphawave in 2017 and has since served as its Senior Vice President of Operations and Chief Operating Officer. Prior to Alphawave he co-founded V Semiconductor Inc. where he was a Director and also Snowbush Microelectronics Inc.

Alphawave came to SemiWiki at the end of 2020 when I did the CEO interview with Tony. I immediately knew that this company would be one to watch and it has not disappointed. Since then we have published 12 articles and two podcasts garnering more than 200k views and listens which is a big number.

After listing on the London Stock Exchange AlphaWave acquired OpenFive, the ASIC division of SiFive, which I wrote about here: Alphawave IP and the Evolution of the ASIC Business.

“With OpenFive, Alphawave now competes in the multibillion dollar ASIC business with the likes of Marvel, who acquired the ASIC business from GF and eSilicon, and Broadcom who has the Avago/LSI Logic ASIC business.

You will also see Alphawave come out with standard products (my opinion) like Marvel and Broadcom putting them in the chip big leagues. Thanks to OpenFive, Alphawave expects to hit $500M in 2024 and I expect them to hit $1B not long after that. Yes, this acquisition is that good and I am sure there are more acquisitions to follow.”

With the name change from Alphawave IP to Alphwave Semi the march to IC products (custom silicon) will begin, absolutely.

John Lofton Holt, Executive Chairman of Alphawave:
“Today we announced a new brand for our company, Alphawave Semi, which reflects our ambition since IPO – to build the leading vertically-integrated semiconductor company focused on connectivity solutions. We are committed to generating shareholder value and we are confident that all of our stakeholders will be rewarded as we successfully execute our long-term strategy and continue to deliver for our customers.”

Tony Pialis, President and Chief Executive Officer of Alphawave:
“We are building a leading connectivity business on the foundations of our high-performance IP. Our focus is on executing our vision with an expanded connectivity portfolio addressing more of our customers’ connectivity needs. With a team of almost 700 employees, we are excited about the opportunities ahead and the long-term potential of the business.”

About Alphawave Semi
Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com

Also Read:

High-End Interconnect IP Forecast 2022 to 2026

Integration Methodology of High-End SerDes IP into FPGAs

Die-to-Die IP enabling the path to the future of Chiplets Ecosystem

 

Posted on

Where there’s Smoke there’s Fire: UCTT ICHR LRCX AMAT KLAC Memory

Where there’s Smoke there’s Fire: UCTT ICHR LRCX AMAT KLAC Memory
by Robert Maire on 01-16-2023 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Stock Market on Fire

-UCTT & ICHR both pre announce ugly QTR & blame memory
-LRCX is the memory “poster child” & most impacted
-This is on top of China & Economic issues & memory specific
-Clearing out inventory is a sign of expected slow recovery

UCTT & ICHR pre-announce ugly quarters

Both UCTT & ICHR that are big suppliers to both Lam and Applied, pre-announced a sharp drop in business and seem to indicate it isn’t just a one and done but longer term issue. Both said that memory related business was the main cause of the miss. Lam is obviously the most memory centric of the equipment OEM’s

That flushing sound is inventory

It sounds like OEMs are flushing inventory and orders for new inventory to reduce their exposure (as they should) . This reduction sounds larger and more severe than prior, short lived downturns or pauses in the industry. This seems to suggest that OEMs are expecting a longer, deeper downturn than in recent past-not just a brief pause.

Sub suppliers are the end of the whip but all on the whip are impacted

Sub suppliers such as UCTT & ICHR are near the end of the whip and thus most volatile but others further up the chain will get hit given the level of impact we see at this part of the food chain.
The chain is: Consumer, Product OEMS, Samsung/Inte/TSMC, equipment OEMS, sub suppliers & raw parts suppliers.

LRCX sounds like a “short”

Lam is the most impacted by the memory industry and is one of the biggest customers of both UCTT & ICHR that just missed badly, likely due to a lot of Lam cancelations. Lam supplies both Samsung and Micron.
This is a lot of smoke surrounding Lam which usually indicates a fire.

Negative news will be obscured by goods in field & backlog

Lam had previously reported billions of dollars of almost finished product sitting in crates in the field waiting on parts or completion. Those dollars sitting in crates and a longer than usual order backlog will obscure the actual drop in business that the company is experiencing especially at the bottom line as much will come in at high margin.

The question to ask and be answered on the conference call is what business would look like without all that built in buffer that softens the initial blow.
The main problem is that the buffer will get used up relatively quickly.
This suggests that Lam will not likely miss the quarter as it can manage through this buffer but forward guide on business may not be as strong.

Other sub suppliers that may have issues

AEIS, Advanced Energy, is, at its core a sub supplier of power assemblies to the semiconductor equipment industry and even though more diversified than UCTT & ICHR will get hit as their semi equipment business is higher margin business. MKSI started out as a sub-supplier but has diversified so much that the impact will be minimal.

AMAT & KLAC to a lesser extent

AMAT & KLAC are not nearly as impacted by memory as Lam but still are, as no one in the business can avoid it. KLA’s backlog is second only to ASML so they should weather this the best of the three with AMAT somewhere between.

The stocks

We find it amusing and typical of Wall St that there are many Strong buys and Buys on LRCX with a couple of market performs but no Sells? Yes, the very long term secular view remains very positive but why own it if its going down and likely to report a poor outlook. I can buy back in later at a cheaper price and catch the long term upside. Everyone is talking about WFE being down 20% or more with memory significantly worse than that. We seem to be in a triple whammy of China, the economy and memory and most analysts remain with buy ratings. We are in the middle of a cloud of smoke but no one is yelling “fire”.

About Semiconductor Advisors LLC‌

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

Samsung Ugly as Expected Profits off 69% Winning a Game of CAPEX Chicken

Micron Ugly Free Fall Continues as Downcycle Shapes Come into Focus

AMAT and Semitool Deja Vu all over again

Micron- “The first cut isn’t the deepest”- Chops production & forecast further

Posted on

Who will Win in the Chiplet War?

Who will Win in the Chiplet War?
by Daniel Nenni on 01-16-2023 at 6:00 am
Categories: Chiplet, Events
1 Comment

Chiplet APEC

The first Chiplet specific conference is coming up which is a milestone in itself. As we know the only thing new about chiplets is the name but when there is a dedicated conference to such a specific thing you know it has officially “arrived”. There is even a cool new tagline: Chiplets make huge chips happen!

“The First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts, and talk to vendors offering a wide variety of products and services.”

The Chiplet Summit (January 24-26th) is brought to us by the folks who do the very successful Flash Memory Summit. There are three full days of conference with a pre conference day on Tuesday and regular conference days on Wednesday and Thursday. Given live conferences of late are back to pre-pandemic levels I would expect a full house. Quite a few companies that work with SemiWiki will be presenting so I of course will be there too. If you are there look me up, it would be a pleasure to meet you.

There is a great keynote line up with some very familiar faces. One of the more notable ones is the Daniel Armburst co-founder of Silicon Catalyst who is speaking on “How Chiplets Can Help You Profit from Chips for America”.

Abstract:

The semiconductor industry has evolved over six decades from its origin in startups, venture capital, and vertically integrated companies to a robustly growing, horizontally integrated and concentrated supply chain. Chiplets are one of the major trends that will shape the future winners and losers and resulting industry structure. Chiplets will also be essential for accelerating startup innovation and addressing designer productivity.

While die aggregation has become a reality for many important companies, replicating that success has yet to be achieved for packaging aggregation of commonly available chiplets. Several critical business model challenges and ecosystem developments are required to get to a vibrant standards-based chiplets world.

With the passage of the $52B CHIPS Act in the U.S. and similar initiatives elsewhere in the world, there should be ample opportunities to accelerate the timelines and benefits for industry, government and academic stakeholders.

So, back to the chiplet war, to me chiplets are all about design enablement: getting designs to wafer faster, cheaper, and with less risk of failure (yield). And who does that really benefit the most? TSMC of course. In fact, design/wafer enablement is what the TSMC OIP is all about.

In order for chiplets to work there must be an ecosystem that documents the provenance of the chiplet and that is what TSMC already does for EDA tools, commercial IP, and other critical parts of design enablement. Nobody is better at ecosystem building than TSMC and it really is like a snowball rolling down Mount Everest.

The semiconductor IP industry will also win big. Chiplets brings royalty IP licensing back into focus. Getting paid per chip really is the IP holy grail and something Wall Street greatly respects. I have personal experience in collecting IP royalty revenue from foundries which was quite a challenge. Arm perfected this model as did the former Artisan Components back in the 1990s. Arm then purchased Artisan for an amazing $900M and the IP royalty model was a key component in the acquisition.

But as I said, getting a royalty agreement is hard enough but collecting those royalties was even harder. With chiplets you will be selling die so it is more of a chip sale than a royalty play. This should simplify the chiplet IP monetization process dramatically and greatly appeal to Wall Street, VCs, and other financial backers of the semiconductor ecosystem, absolutely.

Also Read:

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

Chiplets UCIe Require Verification

Synopsys Crosses $5 Billion Milestone!

Podcast EP137: The International Impact of Accellera’s Work

Podcast EP137: The International Impact of Accellera’s Work
by Daniel Nenni on 01-13-2023 at 10:00 am

Dan is joined by Lu Dai who is currently a Senior Director of Technical Standards at Qualcomm. Previously he was Senior Director of Engineering, leading Qualcomm’s SoC design verification team and front-end methodologies and initiatives. Lu is Chair of Accellera Systems Initiative and serves on the Board of Directors at RISC-V International.

Lu discusses the various standards efforts he is involved with through Accellera and its collaboration with other worldwide organizations such as the IEEE.  He reviews some of the organization’s accomplishments over the past year, including new work on IP security, updates to IP-XACT and a new focus on AMS standards. Looking ahead, there will be more live DVCon events around the world, and new focus on functional safety and clock domain crossings, among others.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

https://accellera.org/

Posted on

CEO Interview: Matt Genovese of Planorama Design

CEO Interview: Matt Genovese of Planorama Design
by Daniel Nenni on 01-13-2023 at 6:00 am
Categories: CEO Interviews, Planorama Design, Semiconductor Services

Matt Genovese

Matt Genovese is the founder and CEO of Planorama Design, bringing over 25 years of career experience in high-tech, spanning semiconductors, hardware, IoT, IT, and software product development.  He has a strong track record of planning, launching, and shipping products that work.  Matt’s company, Planorama Design, is a software user experience design professional services company, designing complex, technical software that is simple and intuitive to use.  Staffed with seasoned engineers and user experience (UX) designers, the company is headquartered in Austin, Texas, USA.

Matt earned a B.S. in Computer Engineering from the Rochester Institute of Technology and an M.S. in Electrical Engineering from The University of Texas at Austin. He began his career at Motorola-Freescale Semiconductor in product & test engineering and moved into design verification of RISC processors and SoCs. Matt has also held product leadership roles for complex and technical software development. As a result of his deep professional experience, Matt strives to “get it right the first time” starting with the software application’s user experience design, down to the hardware at the bottom of the stack.  Planorama helps drive product development processes that create products that work out of the gate.

What is the backstory of Planorama Design?

A quote from Susan Dray are words to live by in the world of product design. She said: “If the user can’t use it, it doesn’t work.” 

I’ve spent my entire career making sure products work, both in the semiconductor industry and in pure software productization. During the first half of my career, as a product & test engineer, then as a functional verification engineer, I had to ensure products worked out of the gate.  After all, when mask sets cost millions, verifying functionality pre-silicon is a business imperative.

That “get it right the first time” mentality carried into the second half of my career in pure software companies – always focused on complex, technical software and SaaS products. Even though software is cheaper to deploy than hardware, executing any kind of redo, especially “down to the chassis”, is still very costly. My experience showed that upfront planning and deep thinking through key requirements and features with an eye for future saved money that would otherwise be spent later on costly redos.

I also noticed how modern software is developed very differently from hardware. Software Agile development processes, user experience (UX) design, and detailed requirements documentation enable rapid, iterative, and efficient software development. These software development concepts have been traditionally absent in the semiconductor industry, which is accustomed to longer, non-iterative hardware design cycles. 

Semiconductor companies are increasingly creating and delivering both chips and software as part of their overall solution. To remain competitive, customer-facing software should meet the same high standards as state-of-the-art semiconductors. Disciplined UX design gives us world-class software that is easy to use for semiconductor customers. Again, ultimately, “if the user can’t use it, it doesn’t work.”

Today I see some in the semiconductor industry are catching on. Intel’s own CTO Greg Lavender recently echoed this same sentiment: “You’re great engineers. You put together this great piece of whatever. Now show me how it’s going to be used from the end-user perspective. Because if we can’t do that, no one’s going to buy the stuff anyway.” His words resonate! They speak to Planorama’s backstory and the overarching mission of my career – it’s what we do here at Planorama Design.

What problems are you solving?

We tackle the three critical challenges encountered when deploying software products: quality of the user experience, time-to-market, and budget.  These problems are just as relevant to semiconductor and hardware companies as they are in pure software businesses.

What does a “user experience quality” problem look like? Like functional bugs in your silicon, a confusing user interface prevents your customers from achieving their objectives, impacting the perceived quality of your products. UX designers may call it a  “usability” problem, but at the end of the day, it’s another quality problem that can degrade the value of your entire solution at best or kill your ability to capture design-ins at worst. Your chips and edge hardware may be superior, but if customers cannot easily build their solution, their time-to-ramp to production delays and the overall success of you and your customer is diminished. You built great hardware; now, design the software that will unlock the value of your technical excellence.

Secondly, we tackle the “time-to-market” problem by ensuring your software developers have all they need to code quickly and accurately.  Software development teams are handed the baton last, before the product goes out the door. Stakes (and attention) are high and as I’ve witnessed, often they have not received the requirements needed to execute efficiently. We’re talking about high-fidelity visual specifications and the business rules, written in well-organized, thorough, “dev-ready” internal product documentation.  When developers can develop and not have to design screens or wait for requirements, products simply get out the door faster.

Third, but not least, deploying software is not an inexpensive proposition.  Development teams are large and costly, so the longer a project takes and the more cycles it has to go through, the more likely a budget will be blown.  Excellent user experience design avoids the inefficiencies that will balloon your dev costs by minimizing the duration of the software project.  Finally, since usable software is intrinsically intuitive, there’s less need for customer support and training, which again reduces long-term costs. UX design is more of a way to reduce costs than spend money!

What makes Planorama’s services unique?

For one thing, it’s the sheer span and the depth of our capabilities. Our team has worked across many verticals to solve all types of problems for our clients.  It turns out the solutions to a vast number of problems have already been solved in other spaces, and we have designed them.  Now combine that with our deep in-house engineering expertise, and we’re able to talk shop with anyone to get the design problem addressed the right way.  Planorama not only has senior user experience designers, but also engineers with computer, electrical, and chemical academic backgrounds.  You won’t need to explain transistors, logic synthesis, edge networking, or AI to us, so we develop domain knowledge very quickly.

Finally, I would paint ourselves as “no-nonsense.”  It’s not our first rodeo, and we’re not trying to win art contests.  We have a mentality of rolling up our sleeves and delivering what our clients need to ship.  Users need interfaces that make sense, developers need solid and complete designs with requirements documentation to code efficiently, and QA needs to validate functionality against a well-organized spec.  That’s what we do so our clients can accelerate to market with a product that delights their customers.

What do you see on the horizon in the semiconductor and hardware space in terms of user experience design?

I’ll summarize what I have observed in the pure software space which I believe is relevant to semiconductor companies today:

Vertical Integration:  Hardware companies are building both the components and the integrated solution, which now includes customer-facing software. For their customers to be successful, the complete solution must be best-in-class quality, including the software that ties it all together.  Just look at what NVIDIA is doing with their enterprise software suite that supports cloud customers who create AI applications, leveraging off the shelf pre-trained AI libraries to support quick build, then deployment, and finally end-to-end management.  Their software ties together the entire solution into an extremely compelling cloud and edge offering.  I’d want to use it!

Digital Transformation:  Existing legacy software needs to meet the expectations of changing customer requirements. For instance, migration from on-premises solutions to the cloud can launch a company ahead of its competition, but the effort also requires new expectations, know-how, and skill sets in both software design and development.

Customer-enablement:  Businesses that purchase and integrate hardware to build solutions require upfront time to do so.  It’s to the advantage of any hardware vendor to enable their customers’ acceleration to market.  Enabling your customers with easy-to-use software to build their own solutions more easily and quickly means they ramp to production and generate revenue sooner.

Purpose-built Products:  We’re seeing specialized solutions that meet business requirements for specific types of customers. In contrast to general-purpose products, these require a solid understanding of the target customers, their users, and use cases.  The entire solution – including the critical software that ties it all together, must be a complete match for their needs.

“New EDA”:  A new wave of EDA tooling is emerging. These new EDA solutions largely aim to address the traditional barriers that made custom ASIC design infeasible for many enterprises.  Companies who cannot afford large IC design departments and budgets can now have another option beyond expensive FPGA implementations.  With intuitive user interfaces crafted to reduce the need for training and support, they are much simpler than traditional EDA solutions while effective for the companies who aren’t pushing the bleeding edge of performance.

I expect to see more semiconductor and hardware companies taking a serious look at integrating user experience design into their software processes.  UX design is already a critical part of pure software productization, not only to create usable products, but getting them to market faster while spending less.  As customers increasingly expect the same world-class user experience from their integrated hardware solutions as they do from their software solutions, companies must recognize the importance of strategically investing in user experience design.  Companies that do will be the winners in the long run, chosen by customers who prefer complete solutions that “work”.

Also Read:

CEO Interview: Dr. Chris Eliasmith and Peter Suma, of Applied Brain Research Inc.

A Five-Year Formal Celebration at Axiomise

CEO Interview: Ron Black of Codasip

Posted on

To EV or NOT to EV?

To EV or NOT to EV?
by Roger C. Lanctot on 01-12-2023 at 10:00 am
Categories: Automotive
7 Comments

1671651657686

It’s anybody’s guess when it comes to future demand for EVs. KPMG is the latest to put a perspective out on the subject – drastically slashing timelines for EV adoption based on a survey of senior industry executives. KPMG says the surveyed executives reported a median expectation for EV adoption by 2030 to 35% of sales from 65% of sales reported a year earlier.

Of course, KPMG knows you can’t forecast demand from surveys. If anyone has been proven wrong regarding consumer interest in and demand for EVs it is the average auto industry executive manufacturing primarily internal combustion vehicles.

These same executives have been begging for some kind of certainty – given their multibillion dollar commitments and the required capital investments to pull off a pivot to EV development and manufacturing. Politicians have done their best to comply with this demand with end-of-combustion-vehicle mandates set to hit by 2035 in various countries and states around the world.

Perhaps not the kind of certainty auto makers actually wanted. In the words of Stellantis CEO Carlos Tavares: “What is clear is that electrification is a technology chosen by politicians, not by industry.”

But the push for certainty and the instinctive reach for incentives has introduced uncertainty and confusion. One set of tax credits ended in the fall in the U.S. only to be replaced by a more confusing and limited offering of incentives that set the stage for a wider range of eligible vehicles when limits are removed in the new year. (This will no doubt be a boon for Tesla, General Motors, Ford, and Volkswagen, among a few others.)

Some editorial comment and details in this Youtube video: https://www.youtube.com/watch?v=-craPSvJWfw&t=267s

Link to government’s list of tax credit eligible EVs with final assembly in North America (SOURCE: Dept. of Energy):  https://afdc.energy.gov/laws/electric-vehicles-for-tax-credit

IRS guidance:  https://www.irs.gov/businesses/plug-in-electric-vehicle-credit-irc-30-and-irc-30d

The incentive gear shift in the U.S. vastly narrowed the range of eligible EVs for the second half of 2022 and raised questions regarding the efficacy of tax-based incentives. (Cars that are eligible almost immediately receive price markups from dealers.) It was hardly a shock – except for Swedes – when the Swedish government suddenly and without notice terminated EV incentives in November.

Maybe in response to the lifting of incentives, Volvo Cars CEO Jim Rowan said he expected electric vehicles to reach price parity with fossil fuel burning vehicles within 2-3 years. J.D. Power’s EV Index points to cost parity for building EVs coming soon, but notes charging infrastructure and vehicle supply limitations cooling consumer demand. J.D. Power nevertheless sees one in five vehicles on the road in the U.S. being an EV by mid-decade – vs. one in 20 today.

The EV doomsday survey from KPMG would suggest a more jaded outlook that will require the support of incentives indefinitely.

In the midst of all this, one can only imagine Toyota CEO Akio Toyoda scratching his head at the EV mania when Toyota continues to offer one of the most reliable, inexpensive, climate friendly, and durable vehicles – the proud Prius hybrid – for a fraction of the prices demanded by competing EVs.

Toyota isn’t wrong to suggest that the rest of the industry has it all wrong regarding electrification. The mere fact that so many taxi fleets and ride hailing drivers worldwide continue to rely on the Prius is a powerful endorsement that is hard to ignore. (For the price of a typical EV one could buy two brand new Priuses.)

What all of these perspectives, forecasts, and insights are forgetting, though, is the elephant in the room: the rapidly ramping onset of Chinese EVs. What was once a nation with dozens of car makers unable to export more than a handful of vehicles globally has rapidly evolved into an EV juggernaut and what will soon be the second largest car exporter globally.

The confusing and off-putting EV incentives in the U.S. – intended to forestall rising Chinese dominance in the sector – has failed to staunch the flow of Chinese EV startups and their steady encroachment on South American, Western European, Southeast Asian and other markets around the world including the U.S. – Volvo, Polestar, anyone?

With solid local supply chains, ample raw material resources, and even technical leadership in next generation battery chemistries, the true wild card in the global EV market is China. China’s ability to compete directly on price may even render domestic production-targeted incentives irrelevant.

The bottom line is that no one really knows how the EV proposition will play out. Incentives are helpful but confusing and undermined by dealer markups. China has the chops to upend the best laid plans of legislators around the world.

In the end, Sweden probably got it right. Remove confusing incentives and let the market find its own level in the context of a long-term objective of phasing out fossil fuel burning vehicles. Trying to time the interest level of consumers in EVs is a fool’s errand matched only by the effort to push consumers into buying EVs. Consumers can do math. When the numbers make sense, they will electrify.

Also Read:

The Smartphone Snitch in Your Pocket

Regulators Wrestle with ‘Explainability’​

Functional Safety for Automotive IP

Don’t Lie to Me

Podcast EP136: Semiconductor Industry Update with Malcolm Penn

Podcast EP136: Semiconductor Industry Update with Malcolm Penn
by Daniel Nenni on 01-11-2023 at 10:00 am

Dan is joined by Malcolm Penn, CEO of Future Horizons. Malcolm is a contributor to SemiWiki and a frequent podcast guest.

Dan and Malcolm discuss what happened in the semi industry last year and what 2023 and 2024 will look like and why. The discussion is a preview to Malcolm’s upcoming Industry Update Webinar on January 17 at 3pm London time, which is 7am PST with a replay available shortly thereafter.

You can register for the webinar here: https://us02web.zoom.us/webinar/register/2616691487856/WN_xYEvDlkzTaejlUeyqI-_6g

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.