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April 1, 2024April 1, 2024

MZ Technologies Enables Multi-Die Design with GENIO

MZ Technologies Enables Multi-Die Design with GENIO
by Mike Gianfagna on 04-01-2024 at 6:00 am
Categories: Chiplet, EDA, MZ Technologies
1 Comment

MZ Technologies is a unique company that enables multi-die design by providing critical planning and analysis tools that sit above the traditional EDA design flow. Chip and package design tools are good at what they do. Given a set of constraints, they will deliver a good result. The question is, what is the right set of constraints? What type of stack (for 3D), what type of interposer (for 2.5D) and what type of placement of blocks and pins will deliver the best result? These are just some of the questions MZ Technologies addresses. The company’s design tool is called GENIO™. I got an opportunity to see a live demonstration of the tool recently. That illuminated a lot about its impact. Read on to see how MZ Technologies enables multi-die design with GENIO.

If you want some background on MZ Technologies and how its products fit in the design flow, you can get that here. You can also get an overview of the GENIO product suite here. As they say, a picture is worth 1,000 words. A live demo has similar power to illuminate concepts. Let’s dig in…

GENIO for 2.5D

Francesco Rossi

Francesco Rossi, engineering manager at MZ Technologies began the demo by developing a 2.5D design consisting of an XPU and four HBM memory stacks. Using simple and intuitive “drag and drop” capabilities and library managers, he configured items such as the four HBM stacks, the XPU, the PHYs for each HBM and a silicon interposer. Bump locations were also defined for the interposer to handle connectivity between components and through the silicon interposer to the package substrate. Connection points on the package were also defined with GENIO in a straight-forward manner.

Below is a screen shot of the graphical representation of the completed stack.

2.5D Stack Configuration

Once the complete stack was defined (package, interposer, devices), connectivity was introduced and optimized. The optimization process examined the fly lines implied by the connectivity to minimize overall fly line length. This will deliver a more optimal starting point for the downstream implementation flow. Consideration was also given to ensure there were no crossovers in the fly lines. The figure below shows the results of this work. All fly lines are displayed. The red items are through-silicon vias (TSVs). These have been either automatically placed or guided by the designer for critical areas.

2.5D Stack with Fly Line Routing

Anna Fontanelli

Anna Fontanelli, founder and CEO at MZ Technologies also joined the demo. She explained that this demo was developed in conjunction with Synopsys to ensure a good fit between GENIO and the implementation tools and IP that it works with. She said that Synopsys DesignWare IP was used for the demo, which interfaced with Synopsys IC Compiler and Custom Compiler. The key point was a good flow between the high-level planning offered by GENIO and the tools and IP that would ultimately implement the final system.

She went on to explain that this design had over 200,000 nets. The interconnect cockpit provided by GENIO delivers substantial new capabilities to manage and optimize a problem of this size. For example, pin groupings can be defined that cross the entire design hierarchy. Fly lines and group of fly lines can be analyzed for average, min and max length. She pointed out that analyzing the design across the full hierarchy, from silicon all the way to the package provides a unique perspective on system performance that is difficult to achieve with conventional approaches.

Using these, and many other capabilities the aspect ratio of the initial design can be examined to ensure an optimal result. Slight changes in aspect ratio and placement can be quickly assessed to find the best result. Anna also explained that estimated resistances can be extracted from the interconnect to drive early static timing analysis.

GENIO for 3D

Marco Cignarella

Marco Cignarella, senior software engineer at MZ Technologies showed how GENIO can be used to define and optimize 3D stacks. A design consisting of multiple chips and memories was used. By changing the stack configuration, the overall interconnect length and number of TSVs can be quickly assessed. Key relationships about the relative placement of components in the 3D stack can be easily specified before optimization begins. This allows global designer perspective to be considered with minimal intervention.

Using these capabilities, the top two or three stack configurations can be quickly identified for further analysis. Below are screen shots of one candidate 3D stack configuration and the associated fly line routing view. A lot of global perspective can be achieved in a short period of time.

3D Stack Configuration

3D Stack with Fly Line Routing

To Learn More

This demo session provided an incredible amount of design perspective and analysis in a short period of time. I am sure many design teams work to develop the optimal configuration for a 2.5D or 3D design using Microsoft Excel and PowerPoint. The data that drives these analyses is often scattered across multiple directories.

The ability to do this work in one “cockpit” with one, verified data source and automated analytics and visualization tools can take a multi-week project down to a day or so, with far better results. If you are considering multi-die design, you need a tool like GENIO. The ways to contact MZ Technologies can be found here. And that’s how MZ Technologies enables multi-die design with GENIO.

Also Read:

MZ Technologies Enables Multi-Die Design with GENIO

How MZ Technologies is Making Multi-Die Design a Reality

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies

Podcast EP214: The Broad Impact of proteanTecs with Noam Brousard

Podcast EP214: The Broad Impact of proteanTecs with Noam Brousard
by Daniel Nenni on 03-29-2024 at 10:00 am

Dan is joined by Noam Brousard, who has over 20 years of diverse technology experience, spanning systems engineering, software development and hardware design. He currently serves as the vice president of Solutions Engineering at proteanTecs, where he helps customers implement on-chip monitoring solutions to address their biggest quality and reliability challenges and optimize their power and performance. Previously, he served as proteanTecs’ vice president of Product, leading the development and commercialization of the company’s multi-disciplinary product portfolio.

Noam discusses the architecture and operation of proteanTecs fine-grained embedded sensing and analysis capabilities and how the technology enhances many aspects of the design, including power, performance, quality and reliability over the device lifetime.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

March 29, 2024September 5, 2024

LIVE WEBINAR: RISC-V Instruction Set Architecture: Enhancing Computing Power

LIVE WEBINAR: RISC-V Instruction Set Architecture: Enhancing Computing Power
by Daniel Nenni on 03-29-2024 at 8:00 am
Categories: Andes Technology, Events, IP, RISC-V

In the dynamic landscape of chip design, two trends stand out as game-changers: the rise of the RISC-V instruction set architecture (ISA) and the advent of Software Defined products. Today, we delve into why these trends are not just shaping the industry but propelling companies like Andes and Menta to the forefront of innovation. Join us for an enlightening webinar where we explore the intersection of these trends and their impact on the semiconductor industry.

SEE REPLAY

RISC-V, a relatively new player in the field, has managed to disrupt a market long dominated by established ISAs. What sets RISC-V apart? One key factor lies in its ability to empower chip designers like never before. With RISC-V, designers can extend the ISA to unlock enhanced computing power, significant performance improvements, power reduction, and reduced costs. Take, for instance, the groundbreaking Meta Training and Inference Accelerator (MTIA). Leveraging Andes Technology Corp.’s RISC-V CPU with vector extensions IP, MTIA showcases the potential of custom extensions to drive innovation in chip design.

Traditionally, adding functionality to a CPU ISA posed significant challenges, often resulting in lengthy design cycles and delays in time to market. However, Andes has revolutionized the process with tools like ACE (Andes Custom Extension) and CoPilot, streamlining the integration of custom extensions into RISC-V CPUs. Now, designers can implement custom changes more efficiently, paving the way for rapid innovation and product development.

But the evolution of chip design doesn’t stop at RISC-V. Enter the era of Software Defined products, where flexibility and adaptability reign supreme. Whether it’s Software Defined Vehicles or configurable electronics in aerospace applications, the need for dynamic adjustments is more pressing than ever. This is where Menta’s embedded Field-Programmable Gate Array (eFPGA) comes into play.

Menta’s eFPGA technology complements RISC-V CPUs with custom extensions, offering unparalleled flexibility across a myriad of use cases. From software-defined radio in telecom to configurable engine management systems in automotive applications, the possibilities are limitless. With Menta’s eFPGA, chip designers can seamlessly adapt to evolving standards, address security vulnerabilities, and optimize performance in real-time.

The synergy between RISC-V and Software Defined products represents a paradigm shift in chip design. By combining the power of customizable ISAs with the flexibility of embedded FPGA technology, Andes and Menta are empowering designers to push the boundaries of innovation. Whether it’s unlocking new capabilities in telecom infrastructure or enhancing imaging and preprocessing in space applications, the possibilities are as vast as the cosmos.

SEE REPLAY

Join us as we dive deeper into the transformative potential of RISC-V and Software Defined products. Discover how these trends are reshaping the semiconductor industry and paving the way for a future where innovation knows no bounds. Don’t miss out on this opportunity to stay ahead of the curve and unlock the full potential of chip design. Register now and be part of the revolution!

Also Read:

LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array

CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology

Extendible Processor Architectures for IoT Applications

March 29, 2024July 18, 2025

Synopsys SNUG Silicon Valley Conference 2024: Powering Innovation in the Era of Pervasive Intelligence

Synopsys SNUG Silicon Valley Conference 2024: Powering Innovation in the Era of Pervasive Intelligence
by Kalar Rajendiran on 03-29-2024 at 6:00 am
Categories: AI, Analytics, Chiplet, EDA, Emulation, IP, Prototyping, Synopsys

AI Powered Hyperconvergence Tools Offerings

After the leadership transition at the top, Synopsys had just a little more than two months before the company’s flagship event, the Synopsys User Group (SNUG) conference. The Synopsys user community and entire ecosystem were waiting to hear new CEO Sassine Ghazi’s keynote to learn where the company is going and its strategic vectors. Sassine, his executive team and the entire company delivered an amazing SNUG 2024.

Right after Sassine took over as CEO, SemiWiki had posted its take on why and how Synopsys is geared for next era’s opportunity and growth. SNUG 2024 with the tagline, “Our Technology, Your Innovation,” provided an excellent avenue for Synopsys to share insights on how the company is enhancing value for all stakeholders in the ecosystem. This was corroborated through numerous testimonials heard throughout the event, from many different companies large, medium and emerging alike.

The event was kicked off with the keynote talk which encapsulated and rounded up the two-day event including several news announcements. An added bonus during the keynote was a special in-person appearance by Jensen Huang, founder and CEO of Nvidia, for an interactive Q&A session with Sassine. The keynote covered the three main trends of increasing silicon complexity, productivity bottleneck and silicon and systems intersection as well as how Synopsys is addressing these with their technology solutions. The following is a synthesis of the keynote session.

Enabling Innovation with IP and EDA Solutions

At the core of Synopsys’ strategy lies its extensive portfolio of Intellectual Property (IP), cultivated with 25 years of industry experience. Synopsys’ IP offerings include a wide range of pre-designed functional blocks and subsystems, covering everything from processor cores and memory controllers to interface IP and analog IP. This IP serves as the foundational building blocks for silicon design, enabling customers to differentiate their products while streamlining the design process. Synopsys remains at the forefront of emerging technologies, ensuring customers have access to the latest IP standards and market trends, thus empowering them to stay ahead of the curve. An example being the company’s announcement at SNUG that it has acquired Intrinsic ID, a leading provider of physical unclonable function (PUF) IP used in SoC design. This addition to Synopsys’ semiconductor IP portfolio provides an additional level of hardware security that is critical for today’s embedded applications and IoT devices.

Synopsys provides a comprehensive suite of Electronic Design Automation (EDA) tools, powered by artificial intelligence (AI). The company’s EDA tools span the entire design flow. From RTL synthesis and simulation to place-and-route and sign-off, Synopsys’ EDA solutions cover every aspect of the design process, enabling designers to optimize their designs for performance, power, and area. By infusing AI into every facet of the design process, Synopsys enables customers to achieve breakthroughs in efficiency and productivity, thereby redefining the boundaries of silicon design. At SNUG, Synopsys announced the development of 3DSO.ai, a new AI-driven capability for 3D design space optimization and architectural exploration using native thermal analysis. The new capability is built into Synopsys 3DIC Compiler to deliver significant productivity gains while also maximizing performance and quality of results. Moreover, with the evolution to heterogenous SoCs, Synopsys’ EDA tools are tightly integrated with its IP portfolio, allowing for seamless interoperability and faster time-to-market.

Convergence of Silicon and Systems Design

With the rise of heterogeneous computing architectures and the proliferation of AI and machine learning workloads, designers must increasingly consider both silicon-level and system-level optimizations when designing their products. As hyperscaler companies invest heavily in silicon development to optimize workloads for specific applications, the traditional boundaries between chip design and system architecture are blurring. Synopsys recognizes the importance of this trend and offers solutions that bridge the gap between silicon and systems design.

Bridging the Gap between Silicon and Systems Design

Synopsys offers a range of solutions that span the entire design continuum, from silicon to systems. At SNUG, Synopsys unveiled two new hardware-assisted verification (HAV) solutions : Synopsys Zebu® EP2, the latest version in the ZeBu EP family of unified emulation and prototyping systems, and Synopsys HAPS®-100 12, Synopsys’ highest capacity and density FPGA-based prototyping system. By providing designers with the tools and methodologies needed to optimize both the silicon and system aspects of their designs, Synopsys enables them to deliver products that meet the demanding performance and efficiency requirements of today’s markets.

Synopsys’ Holistic Approach

As discussed above, Synopsys’ response to the three main trends is characterized by its holistic approach. Rather than focusing on individual components or stages of the design process, Synopsys offers a comprehensive suite of solutions, or stack, that spans the entire design flow, from concept to production. This integrated approach enables designers to seamlessly transition between different stages of the design process, ensuring continuity, efficiency, and accuracy at every step. By working closely with industry partners, customers, and academic institutions, Synopsys is able to stay at the forefront of emerging technologies and trends. This collaborative ecosystem approach not only fosters knowledge sharing and best practices but also drives innovation and accelerates time-to-market for new products and technologies.

Summary

From tackling silicon complexity to embracing the convergence of silicon and systems design, Synopsys is at the forefront of shaping the future of technology. With its extensive portfolio of IP and EDA solutions powered by AI, coupled with a commitment to innovation and collaboration, Synopsys empowers the designer community to think and operate holistically. Designers can easily navigate the complexities of silicon design and deliver breakthrough products that drive the industry forward. From software-driven architecture exploration to hardware-assisted verification, Synopsys provides customers with the tools needed to navigate the convergence of silicon and systems design.

As the semiconductor landscape continues to evolve, Synopsys remains steadfast in its mission to drive technological advancement and enable innovation for years to come. Below are some recent announcements relating to the topic of this keynote.

Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley

Synopsys Expands Semiconductor IP Portfolio With Acquisition of Intrinsic ID

Jensen Huang’s special appearance for an interactive Q&A during Sassine’s keynote talk at SNUG 2024 was centered around the following announcement and the two companies’ decades long working relationship.

Synopsys Showcases EDA Performance and Next-Gen Capabilities with NVIDIA Accelerated Computing, Generative AI and Omniverse

Also Read:

2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification

Synopsys Enhances PPA with Backside Routing

Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips

March 28, 2024March 27, 2024

Ultra-low-power MIPI use case for streaming sensors

Ultra-low-power MIPI use case for streaming sensors
by Don Dingee on 03-28-2024 at 10:00 am
Categories: IP, Mixel

Mixel D PHY TX+ for ultra-low-power MIPI streaming sensors

MIPI built its reputation on the efficient streaming of data from camera sensors in mobile devices. It combines high-speed transfers with balanced power consumption, helping extend battery life while providing the responsiveness users expect. However, high speed is not the only mode of operation for a MIPI interface – specifications also enable low power modes for slower data transfers, going to an ultra-low-power shutdown state when data communication is inactive. These low-power modes are gaining more attention as MIPI-based cameras see adoption in automotive, IoT, augmented and virtual reality (AR and VR), industrial, and medical applications. A new white paper from Mixel jointly authored with ams-OSRAM outlines an ultra-low-power MIPI use case for streaming sensors.

Borrowing a proven power management concept

The idea behind various power modes in power-sensitive applications isn’t new. Commercial microcontrollers specify modes like full-on, doze, nap, sleep, and deep-sleep, intending that staying in a lower-power mode as much as possible conserves power. Low-duty-cycle operation often matches sensor applications with lower sample rates and periodic data bursts. Work like computations and data transmission happens around each burst, returning to sleep between bursts. The result is a much lower average power consumption.

Streaming sensors, like digital image sensors, pose a different problem. Delivering video for human consumption requires more pixels and faster frame rates; otherwise, the experience becomes uncomfortable to watch. Higher resolution, higher frame rate video is costly – with a more powerful SoC to sample, process, and transmit the stream. SoC designers can use clock and power gating techniques to shut down IP blocks when they are unneeded, but when the video stream is on, there seems to be no choice except to use more power.

In many sensor applications, the point is for humans not to watch the streaming video 24/7. The sensor should be smart enough to monitor a scene with nothing of interest until a moment when something starts happening. A dual-context sensor can lower frame rate, resolution, and MIPI transfer rates, shifting into full-power mode only when a change occurs, such as motion. Managing event detection creates a massive power-saving opportunity, maybe 20x or more.

Changing lanes of the MIPI interface

MIPI architects anticipated scenarios like these when they wrote the MIPI specifications. Compliant IP blocks have both a high-speed and low-power lane, with the latter running at a fraction of the data rate. Control logic external to the IP block determines which lane to use.

Mixel MIPI IP achieves remarkable efficiency in any operating mode. For ams-OSRAM, Mixel customized its D-PHY TX+ solution, incorporating D-PHY v 2.1 and CSI-2 v 1.3 functions in a single IP block. In high-speed mode (HS-TX in the diagram), the lane runs at 1.5Gbps, while in low-power mode (LP-TX in the diagram), the lane shifts down to 10Mbps. If more throughput is needed, a 4-lane version is available. Built-in self-test (BIST) logic in the hard macro and CIL RTL exercises both modes, providing 100% test coverage for the block. Mixel indicates the customized D-PHY TX+ uses 30% less area than the comparable D-PHY Universal configuration and reduces leakage power by 40%.

ams-OSRAM took power savings further in their single-chip Mira050 sensor with an active pixel array on-chip by coordinating the sensor resolution sampling, frame rate, MIPI modes, and clock rates. Their fast-switching controller helps their image sensor go from full-on streaming using 75mW to total standby using only 60uW, and they indicate their reliable motion detection with a novel tiling algorithm (described in-depth in the white paper) is possible using around 3mW.

More use cases for ultra-low-power MIPI ahead

Ultra-low-power MIPI streaming sensors open use cases like home security cameras, consumer robotics, e-door locks, and AR/VR wearables. As Mixel puts it, “Any use case combining the elements of a small physical footprint and reduced power consumption yet requiring quality image processing for object classification and event detection can benefit from MIPI integration.” Mixel combines high-speed transfer capability with low-power modes, smaller footprints, reduced power, and increased testability in its MIPI IP solutions.

Learn more about the ams-OSRAM approach to ultra-low-power MIPI in the Mira050 with the Mixel MIPI D-PHY IP in this white paper:

MIPI Deployment in Ultra-low-power Streaming Sensors

March 28, 2024April 19, 2024

Arm Automotive Update Stresses Prototyping for Software Development

Arm Automotive Update Stresses Prototyping for Software Development
by Bernard Murphy on 03-28-2024 at 6:00 am
Categories: Arm, Automotive, IP

If you were at all uncertain about auto OEM development priorities, the answer is becoming clear: to accelerate/shift left automotive software development and debug. At 100M lines of code and accelerating, this task is overshadowing all others. A recent Arm update from Dipti Vachani (SVP and GM for the Automotive Line of Business) led with their new emphasis on support for virtual prototyping for software development. Very interesting given Accellera’s recent update on Federated Simulation as an intended standard for whole-car software simulation (among other objectives). I have also written recently about increasing hardware complexity in zonal controllers and elsewhere, each requiring complex software services, further amplifying the software challenge. All our new tech goodies will amount to little if the software to coordinate the whole system cannot be developed in parallel.

Virtual prototyping solutions

Breaking with the standard Arm announcement flow, Dipti started her update here rather than on new cores (of which they have an abundance). I find this significant; not a token move to supporting software dev shift-left but the leading theme. Which is not surprising because to really shift left the whole automotive stack, firmware, middleware, and applications across all subsystems in the car must come together in parallel with the hardware.

Also of interest, Arm see this digital twin running in the cloud. I sense a trend. I would imagine that partners in the stack can more easily collaborate in this way against an evolving digital twin. But also, per Dipti, software developed in Arm-based cloud instances (Graviton or Ampere for now) will be automatically portable to the Arm-based hardware platforms in the car. Sneaky. Arm is leveraging its established strength in the cloud to push an Arm preference into cars. Even more so if the hardware architecture leverages CSS instances (more on that later) for high performance compute applications. As evidence that this isn’t just talk, she cites the AUTOWARE open autonomous stack (on the right of the above figure), containerized in Amazon AWS instances. Further she adds that this capability can shorten the OEM system development cycle by up to 2 years.

Pretty compelling, though we should remember compute in a car is not just based on Arm technology. In-vehicle infotainment may run on a Qualcomm chip. Sensing, object detection and sensor fusion for vision, lidar and radar will run on complex AI pipelines using a variety of DSP, AI accelerator, and GPU functions along with communications. A complete solution to prototype software for the full car system will likely still need something like the Accellera Federated Simulation standard connecting virtual models from multiple sources in addition to Arm’s initiatives.

New IP options for automotive

Plenty of new info here around extension to the Arm Automotive Enhanced (AE) family. Neoverse from the infrastructure product line has now been added to the AE portfolio as Neoverse V3AE, based on the high-performance V series already adopted in cloud datacenters. Applications are expected to be big in central controllers especially for software-defined vehicles. Arm has now announced that Nvidia Thor (aimed at the central controller) is based on this platform.

Cortex A720AE and 520AE add new few features in support of ASIL B and D certification, and provide cluster configurability between lock modes for safety and split modes for performance. Cortex R82AE extends real-time capability with 64-bit operation and 8 core clusters in support of safety islands while the Mali C720AE ISP adds more support and configurability for human vision and computer vision pipelines. All supporting ASIL B and D requirements and features of course (ASIL B and D seem to be the only ASIL standards mentioned these days. Whatever happened to A and C?)

The final important piece of news in this announcement is that the Arm automotive LOB is now working on CSS (compute subsystem) cores for the AE product line. If you don’t know anything about CSS, these are preconfigured subsystems of Arm cores developed as a customizable compute subsystem, verified, validated, and PPA-optimized by Arm. CSS was first introduced for Neoverse. Arm finds these pre-designed and optimized subsystems are attractive to system designers on a deadline who don’t feel a need to keep re-inventing compute subsystems. I would bet auto system designers feel the same way. Automotive CSS is expected to become available in 2025.

Takeaways

My first takeaway is building support for automotive digital twins, running in the cloud. Whether in a single container for Arm-centric platforms or in multiple containers orchestrated by a Kubernetes or similar will depend on how soon the Accellera standard may appear.

My second takeaway is that Arm has an interesting opportunity to extend its hegemony in cloud-based platforms to automotive platforms as well, simply by virtue of running on the same instruction set architecture in both domains.

You can read the press release HERE.

March 27, 2024March 27, 2024

2024 Outlook with Srinivasa Kakumanu of MosChip

2024 Outlook with Srinivasa Kakumanu of MosChip
by Daniel Nenni on 03-27-2024 at 10:00 am
Categories: Semiconductor Services

MosChip is a publicly traded company founded in the year 1999, they offer semiconductor design services, turnkey ASIC, software services, and end-to-end product engineering solutions. The company headquartered in Hyderabad, India, with five design centers and over 1300 engineers located in Silicon Valley (USA), Hyderabad, Bengaluru, Ahmedabad, and Pune. MosChip has over two decades of track record in designing semiconductor products and SoCs for computing, networking, and consumer applications. Also, MosChip has developed and shipped millions of connectivity ICs.

Tell us a little bit about yourself.
Hello, I’m Srinivasa Kakumanu, commonly known as KS. I’ve been in the semiconductor industry for over 28 years now. One of my notable accomplishments was co-founding First Pass Semiconductors Pvt Ltd, a prominent VLSI design services organization established in December 2010. Throughout my illustrious career, I have played a key role in leading numerous ASIC tape-outs across the Communication, Networking, Consumer, and Computing sectors.

Under my leadership, First Pass experienced significant growth, evolving into a thriving organization boasting more than 210 employees by FY18. This remarkable journey culminated in the acquisition of First Pass by MosChip in July 2018, all the while maintaining profitability since inception. Following the acquisition, I was responsible for the role of heading the Semiconductor Business Unit at MosChip, steering it to remarkable heights.

Before my tenure at First Pass, I held the position of General Manager for the VLSI group at Cyient (formerly known as Infotech Enterprise) in India. My career also includes stints with notable organizations such as TTM Inc. in San Jose, US; TTM India (both were acquired by Infotech in September 2008) Pvt. Ltd. in Hyderabad, India; Ikanos Communications in Fremont, US; QualCore Logic Ltd in India, and HAL in Hyderabad, among others.

I also maintain my professional education commitment by actively teaching Digital Design and Physical Design at MosChip Institute of Silicon Systems Pvt. Ltd, a training institute that I co-founded, which was subsequently acquired by MosChip in July 2018. My international experience includes a seven-year tenure in the United States between 2000 and 2007, where I contributed to TTM Inc. and Ikanos Communications.

What was the most exciting high point of 2023 for your company?
MosChip has reached new heights in the year 2023, with some remarkable achievements. Firstly, we were honored to be recognized among India’s Top 150 Growth Champions and Asia-Pacific’s Top 500 high-growth companies by institutions like the Economics Times, Financial Times, and Statista. This recognition shows our ongoing dedication to excellence and innovation in the semiconductor industry. Adding to this, On March 31, 2023, Softnautics, a semiconductor and software AI solutions company situated in California, was acquired by MosChip Technologies. This acquisition made us more powerful in the software sector and strengthened our portfolio and capabilities, setting us up for worldwide success. We also welcomed Dr. Naveed Sherwani, a veteran of the semiconductor industry, to our Board of Directors with great pleasure. His knowledge will surely help us make better strategic decisions and drive our company forward.

On top of that, being recognized by Qualcomm as the most valuable supplier in the software category for 2022 confirmed our commitment to providing high-quality solutions and forming solid partnerships. Also, Receiving the EE Times Asia Awards 2023 for the Most Influential Corporate in ASIA consecutively for 2 times was a humbling affirmation of our semiconductor industry excellence.

These milestones of 2023 motivate our determination to continue pushing boundaries, driving growth, and making a positive impact in the semiconductor and software sectors.

What was the biggest challenge your company faced in 2023?
The biggest challenge we faced in 2023 was a shortage of qualified chip design engineers in India’s semiconductor industry. The industry’s slow pace and hiring challenges triggered the situation. Despite increasing growth, hiring and finding skilled professionals, especially senior technical leaders, was tough. This challenge restricted our capacity to meet industry demands but with my team and support from the other leaders, we made it through.

How is your company’s work addressing this biggest challenge?
To address this challenge, MosChip has taken significant initiatives to develop new talent in the semiconductor and software fields with our indigenous institute for finishing schools, the “MosChip Institute of Silicon Systems (M-ISS)” which I co-founded and later on MosChip acquired, where we educate and develop aspiring chip design and software engineers, providing them with the training and experience with hands-on experience on the tools that industry professionals use to get them ready for the market. By cultivating these talents through our institute, we can close the skill gap and contribute to the growth and sustainability of India’s ecosystem.

What do you think the biggest growth area for 2024 will be, and why?
From my perspective, the semiconductor and software (both Digital Engineering and Device Engineering) market is expected to expand significantly this year. On the semiconductor front, next-generation memory technologies such as MRAM, ReRAM, HMC, and HBM have moved from studies to industrialization, with leading foundries and integrated device manufacturers (IDMs) qualifying STT MRAM technology for a wide range of applications including power-efficient MCU/SoC chips, ASIC products, IoT devices, wearables, and CMOS image sensors. On top of that, the system design market is predicted to expand significantly in 2024, led by increasing consumer demand for electric vehicles (EVs). Plus, it is expected that there will be a significant increase in various sectors such as telecommunications, healthcare, industrial IoT, consumer electronics, military, and aerospace. Emerging trends like Chiplets, RISC-V, and AI/ML present exciting opportunities for innovation, which will help MosChip maintain its position as a leader in the industry. This will contribute to the overall growth of the semiconductor, software, and systems industries.

Reference – https://www.marketsandmarkets.com/Market-Reports/global-semiconductor-industry-outlook-201471467.html#:~:text=MRAM%20is%20set%20to%20dominate%20the%20next%2Dgeneration,have%20reached%20commercialization%20after%20extensive%20R&D%20efforts.

https://www.linkedin.com/pulse/embedded-systems-market-growth-trends-forecast-2024-l0cxf/

How is your company’s work addressing this growth?
We are actively tackling the significant increase expected in the semiconductor, software, and systems markets by 2024. We devote ourselves to technological advancement to enhance next-generation memory technologies, collaborating with industry leaders to ensure our products exceed strict requirements. With the recent acquisition of Softnautics, we are deepening our expertise in Digital Engineering and Device Engineering and positioning ourselves to take advantage of opportunities in both areas. Overall, our strategic activities are aimed at capitalizing on growth prospects and strengthening our position as a significant leader that can lead us to conquer the semiconductor, software, and systems industries.

Will you attend conferences in 2024? Same or more?
Yes, we plan to make our conference attendance more than what we did earlier to cover our major geographies to meet the customers from USA, India, & Europe. Unlike the previous focus on semiconductor-specific events, We are now looking for more events covering Semiconductors, Product Engineering & AI/ML, etc. Although we value the importance of networking and staying up to date with industry developments at these events, our decision to attend will be based on how relevant the conference is to our company’s goals and priorities for the year.

Additional questions or final comments?
As we look ahead, we want to highlight our incomparable dedication to our customers and stakeholders. We focus on offering high-quality solutions and maintaining strong relationships that create mutual success. Our commitment to customer satisfaction and exceeding expectations is at the bottom of everything we do. As we come up with ever-evolving solutions for the semiconductor, software, and systems industries, our customer-centric approach will stay constant, ensuring that we remain a trusted partner and industry leader for many years to come. We firmly believe that our employees are our biggest asset and as such, we continuously prioritize their development and welfare.

Also Read:

CEO Interview: Larry Zu of Sarcina Technology

CEO Interview: Michael Sanie of Endura Technologies

Outlook 2024 with Dr. Laura Matz CEO of Athinia

March 27, 2024April 19, 2024

Fault Simulation for AI Safety. Innovation in Verification

Fault Simulation for AI Safety. Innovation in Verification
by Bernard Murphy on 03-27-2024 at 6:00 am
Categories: AI, Automotive, Cadence, EDA

The Innovation

This month’s pick is SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. This article was published in the 2023 Great Lakes Symposium on VLSI. The authors are from the Karlsruhe Institute of Technology, Germany.

ISO 26262 requires safety analysis based on FMEDA methods using fault simulation to assess sensitivity of critical functions to transient and systematic faults, and the effectiveness of mitigation logic to guard against errors. Analysis starts with design expert understanding of what high-level behaviors must be guaranteed together with what realistic failures might propagate errors in those behaviors.

This expert know-how is already understood for conventional logic and software but not yet for AI models (neural nets) and the accelerators on which they run. Safety engineers need help exploring failure modes and effects in AI components to know where and how to fault models and hardware. Further that analysis must run at practical speeds on the large models common for DNNs. The authors propose a new technique which they say runs much faster than current methods.

Paul’s view

A thought provoking and intriguing paper: how do you assess the risk of random hardware faults in an AI accelerator used for driver assist or autonomous drive? AI inference is itself a statistical method, so determining the relationship between a random bit flip somewhere in the accelerator and an incorrect inference is non-trivial.

This paper proposes building a system that can “swap in” a real RTL simulation of a single layer of a neural network, an otherwise pure software-based inference of that network in PyTorch. A fault can be injected into the layer being RTL simulated to assess the impact of that fault on the overall inference operation.

The authors demonstrate their method on the Gemmini open-source AI accelerator running ResNet-18 and GoogLeNet image classification networks. They observe each element of the Gemmini accelerator array has 3 registers (input activation, weight and partial sum) and a weight select signal, together 4 possible types of fault to inject. They run 1.5M inference experiments, each with a random fault injected, checking if the top-1 classification out of the network is incorrect. Their runtime is an impressive 7x faster than prior work, and their charts validate the intuitive expectation that faults in earlier layers of the network are more impactful than those in deeper layers.

Also, it’s clear from their data that some form of hardware safety mechanism (e.g. triple-voting) is warranted since the absolute probability of a top-1 classification error is 2-8% for faults in the first 10 layers of the network. That’s way too high for a safe driving experience!

Raúl’s view

The main contribution of SiFI-AI is simulating transient faults in DNN accelerators combining fast AI inference with cycle-accurate RTL simulation and condition-based fault injection. This is 7x faster than the state of the art (reference 2, Condia et al, Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs). The trick is to simulate only what is necessary in slow cycle-accurate RTL. The faults modeled are single-event upset (SEU), i.e., transient bit-flips induced by external effects such as radiation and charged particles, which persist until the next write operation. To find out whether a single fault will cause an error is especially difficult in this case; the high degree of data reuse could lead to significant fault propagation, and fault simulation needs to take both the hardware architecture and the DNN model topology into account.

SiFI-AI integrates the hardware simulation into the ML framework (PyTorch). For HW simulation it uses Verilator, a free and open-source Verilog simulator, to generate cycle accurate RTL models. A fault controller manages fault injection as directed by the user, using a condition-based approach, i.e., a list of conditions that avoid that a fault is masked. To select what part is simulated in RTL, it decomposes layers into smaller tiles based on “the layer properties, loop tiling strategy, accelerator layout, and the respective fault” and selects a tile.

The device tested in the experimental part is Gemmini, a systolic array DNN accelerator created at UC Berkeley in the Chipyard project, in a configuration of 16×16 processing elements (PE). SiFI-AI performs a resilience study with 1.5 M fault injection experiments on two typical DNN workloads, ResNet-18 and GoogLeNet. Faults are injected into three PE data registers and one control signal, as specified by the user. Results show a low error probability, confirming the resilience of DNNs. They also show that control signal faults have much more impact than data signal faults, and that wide and shallow layers are more susceptible than narrow and deep layers.

This is a good paper which advances the field of DNN reliability evaluation. The paper is well-written and clear and provides sufficient details and references to support the claims and results. Even though the core idea of combining simulation at different levels is old, the authors use it very effectively. Frameworks like SciFI-AI can help designers and researchers optimize their architectures and make them more resilient. I also like the analysis of the fault impact on different layers and signals, which reveals some interesting insights. The paper could be improved by providing more information on the fault injection strategy and the selection of the tiles. Despite the topic being quite specific, overall, a very enjoyable paper!

March 26, 2024March 25, 2024

A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs

A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs
by Daniel Payne on 03-26-2024 at 10:00 am
Categories: IP, Mirabilis Design

Demo Chiplet System with CPU, DSP, GPU, IO, AI

During the GOMACTech conference held in South Carolina last week I had a Zoom call with Deepak Shankar, Founder and VP Technology at Mirabilis Design Inc. to ask questions and view a live demo of VisualSim – a modeling, simulation, exploration and collaborative platform to develop electronics and SoCs. What makes VisualSim so distinctive is that it comes bundled with about 500 high-level IP blocks ready to use, including 35 ARM processors, some 100 processors, and over 30 different interconnects. Users of VisualSim quickly connect these IP blocks together visually to create their systems, complete with networks. An automotive designer can model the entire network, including 5G communications, Ethernet, SDA and OTA updates with VisualSim.

A high-level model allows for quickest architectural exploration and making architectural trade-offs, way before implementation even begins with RTL code. You can model complex activities like a bus, memories and even cache, measuring things like end-to-end delays and latency. Engineers can measure what their cache hit/miss ratio is, and what happens with requests to L2 caches. All the popular network protocols are modeled: AXI, CHI, CMN600, Arteris NOC, UCIe, etc.

With this modeling approach an architect can model an SoC, complete aircraft or automotive system, and then begin to measure it’s performance to see if it meets the requirements. VisualSim is a multi-domain simulator that can integrate analog, software, power systems, digital and networking into a single model.

For the live demo Deepak showed me a chiplet-based design that had separate chiplets for the DSP, GPU, AI processor and CPU all connected together using UCIe, and each IP block was parameterized to allow for customization and exploration.

Demo Chiplet System with CPU, DSP, GPU, IO, AI

Pushing into the UCIe block there was an IP called a UCIe switch, and a user can customize this block with five parameters, all at a high level.

UCIe Switch parameters

A router IP block had 10 parameters for customization.

Router parameters

To find each IP block there was a scrollable list on the left-hand side of the GUI, with each family of IP in the library. In a matter of seconds you can browse, select and start customizing an IP.

IP block list

In VisualSim you are connecting each IP in the dataflow, staying at a high level. The next live demo was for a multimedia system design, and to simulate 20 ms took about 15 seconds of wall time, running on a laptop. While the simulation is running you can view the system performance as instantaneous power, measure pipeline utilization, cache utilization, memory usage, and even view a timing diagram. This real time simulation triggered 7.5 million events, and the customer built this model in under 2 weeks, which included the entire SoC.

Multimedia system, timing diagram

Another customer example that Deepak mentioned include 45 masters and was completed in about 4 weeks, fully tested.

You can look inside any of the IP blocks and analyze metrics like pass/fail, then understand why it failed. There’s even an AI engine to help analyze data more efficiently, like finding a buffer overflow which caused a failure. While your model is running there are analytics captured to help measure system performance and identify architectural bottlenecks.

VisualSim is updated twice per year, and then there are patch updates for when new IP blocks are added. An architect defines requirements in an Excel file, with metrics like latency limits and buffer occupancy.

Requirements file

Users of VisualSim can define the range of payload size in terms of bytes, speed ranges and preferred values. Your system model can be swept across the combinations to find the best set of parameters. The simulator even understands how to explore the min, max, and preferred values. You get to define which system parameters will be explored. A multimedia system demo was shown next and then simulated live.

Multimedia System

For an FPGA block you choose the vendor and part number, and then you can see the latency for each Task and the channel statistics of the NOC after a simulation has been run. A power plot was shown for 1 second of operation when using Xilinx Versal parts.

Power Plot

All of the live demos were being run on a Windows laptop. Other supported OSes are: Unix, Mac. Running VisualSim requires a minimal HW infrastructure, because the models are high level.

VisualSim users receive over 500 examples that are pre-built to help get you started quickly, like a complete communication system with an Antenna, Transceiver, FPGA with baseband, and Ethernet interface. System architects using VisualSim can collaborate with all the low-level specialists, like RTL designers.

System-level trade-offs can be modeled and evaluated, like:

Changing from 64-QAM to QPSK modulation
Faster to slower processor
Changing Ethernet specs

If you start with VisualSim to model, implement, then measure, expect to see 95% accuracy compared to RTL implementation results. The promise of using high level models is to eliminate performance issues prior to implementation or integration. There really is no coding required for an entire system model.

Mirabilis has 65 customers worldwide so far and some 250 projects completed. Some of the well-known clients include: NASA, Samsung, Qualcomm, Broadcom, GM, Boeing, HP, Imagination, Raytheon, AMD, Northrup Grumman.

Summary

In the old days a systems designer may have drawn out their ideas on a napkin while eating at a restaurant, and then go back to work and cobble together some Excel spreadsheets with arcane equations to create a model. Today there’s a new choice, and that’s giving VisualSim from Mirabilis a try. You can now model an entire system in a just a few weeks, along with making architectural trade-offs while running actual simulations, all before getting into detailed implementation details.

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March 26, 2024January 20, 2025

Weebit Nano Brings ReRAM Benefits to the Automotive Market

Weebit Nano Brings ReRAM Benefits to the Automotive Market
by Mike Gianfagna on 03-26-2024 at 6:00 am
Categories: Automotive, Events, IP, Weebit Nano
1 Comment

Non-volatile memory (NVM) is a critical building block for most electronic systems. The most popular NVM technology has traditionally been flash. As a discrete part, the technology can be delivered in various form factors. For embedded applications flash presents scaling challenges, however. A new NVM technology developed by Weebit Nano is called ReRAM. Sometimes called RRAM, this approach stores bits as resistance vs. the typical approach of using charge that is prevalent in other memory technologies. NVM is used in many parts of automotive systems, as shown in the diagram at the top of this post. The problem is automotive systems present many challenges around things like operating temperature, safety and reliability. Using ReRAM for embedded applications has been hampered by these hurdles, until recently. Read on to see how Weebit Nano brings ReRAM benefits to the automotive market.

Weebit Nano Opens Access to Automotive Applications

Back in November of last year, Weebit Nano announced that its ReRAM IP achieved high temperature qualification in SkyWater Technology’s 130nm CMOS (S130) process. The announcement detailed qualification up to 125 degrees Celsius – the temperature specified for Grade-1 automotive applications. This temperature range also opens up application for industrial, aerospace and other high-temp applications. You can read the details of the announcement here.

Last month, the company raised the bar on automotive access by detailing high reliability and endurance at extreme temperatures and after extensive cycling. Specifically, high endurance was demonstrated at 100K flash-equivalent cycles and high-temperature stability was demonstrated at 150 degrees Celsius lifetime operation, including cycling and retention. The details are shown in the image, below. This clearly moves ReRAM much closer to mainstream use in automotive applications.

Image: Resistance distribution after 100K cycles at 150C. The Weebit performance demonstrates good BER throughout the entire 100K cycles at hot temperatures.

Coby Hanoch, Weebit Nano’s CEO commented, “The performance levels we’re achieving align with requirements specified by automotive companies. Demonstrating the resilience of Weebit ReRAM under these conditions will continue to enhance our position in this domain. Our latest results reaffirm the viability of Weebit ReRAM for use in microcontrollers and other automotive components, as well as numerous other applications requiring high-temperature reliability and extended endurance. Weebit ReRAM is ideal for these applications, offering advantages including ease of integration, cost effectiveness, power efficiency and tolerance to radiation and electromagnetic fields.”

You can read the full text of the announcement here.

A Closer Look at the Technology and the Challenges

According to the International Roadmap for Devices and Systems, 2022 Edition:

One challenge is the need of a new memory technology that combines the best features of current memories in a fabrication technology compatible with CMOS process flow and that can be scaled beyond the present limits of SRAM and FLASH.

Weebit Nano’s ReRAM technology offers a very cost-effective solution to this NVM need. Some specifics of the technology include:

Two-mask adder
- Very few added steps compared to other NVM technologies
- Lower wafer cost than competing NVM technologies
Fab-friendly materials
- No contamination risk, No special handling, etc.
Using existing deposition techniques and tools
- Easy to integrate into any CMOS fab
BEOL technology
- Stack between any two metal layers
- No interference with FEOL – Easier to embed with existing analog and RF circuits
- Easy to scale from one process variation to another

Some of the growing needs for emerging automotive NVM application include code storage, trimming and data logging. Weebit ReRAM delivers high-temperature reliability, immunity to EMI, endurance, fast switching speed, longevity, and secure operation. And the technology can scale to the most advanced process nodes.

Automotive chips have unique requirements, such as design for safety, security and longevity. Devices must be reliable against extreme temperatures, EMI, vibration, and humidity. Fast boot, instant response, frequent over-the-air updates must also be supported. All these requirements mean advanced process nodes are adopted quickly, and this is where Weebit Nano’s technology shows great promise.

General ICs are qualified according to JEDEC standards – this is the baseline for consumer application markets. The automotive industry follows AEC-Q100 standards (Stress Test Qualification for Integrated Circuits). For automotive qualified ICs, tests are much stricter than those of an industrial or commercial IC. These stringent qualification tests assure reliable operation and long lifetimes in harsh automotive environments.

This is why Weebit Nano’s advanced testing work is so significant for automotive applications. The technology is also relevant for a wider range of applications, as shown in the figure below.

ReRAM Addresses a Broad Range of Application Requirements

To Learn More

You can learn more about the benefits of ReRAM technology here. You can also learn about the application of Weebit Nano’s ReRAM to power management here. WeeBit Nano recently presented at the recent IEEE Electron Devices Technology and Manufacturing (IEEE EDTM) Conference. You can view this presentation here. And that’s how Weebit Nano brings ReRAM benefits to the automotive market.