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Tensilica Processor Cores Enable Sensor Fusion For Robust Perception

Tensilica Processor Cores Enable Sensor Fusion For Robust Perception
by Kalar Rajendiran on 06-22-2023 at 6:00 am
Categories: AI, Cadence, EDA, IP

Tensilica DSPs

While sensor-based control and activation systems have been around for several decades, the development and integration of sensors into control systems have significantly evolved over time. Early sensor-based control systems utilized basic sensing elements like switches, potentiometers and pressure sensors and were primarily used in industrial applications. With rapid advances in electronics, sensor technologies, microcontrollers, and wireless communications, sensor-based control and activation systems have become more advanced and widespread. Sensor networks, Internet of Things (IoT) platforms, and wireless sensor networks (WSNs) further expanded the capabilities of sensor-based control systems, enabling distributed sensing, remote monitoring, and complex control strategies.

Today, sensor-based control and activation systems are integral components in various fields, including industrial automation, automotive systems, robotics, smart buildings, healthcare, and consumer electronics. They play a vital role in enabling intelligent and automated systems that can adapt, respond, and interact with the environment based on real-time sensor feedback. With so many applications counting on sensor-based activation and control, how to ensure robustness, accuracy and precision from these systems? This was the context for Amol Borkar’s talk at the recent Embedded Vision Summit conference in Santa Clara, CA. Amol is a product marketing director at Cadence for the Tensilica family of processor cores.

Use of Heterogeneous Sensors

Heterogeneous sensors refer to a collection of sensors that are diverse in their sensing modalities, operating principles, and measurement capabilities and offer complementary information about the environment being monitored. Image sensors, Event-based image sensors, Radar, Lidar, Gyroscopes, Magnetometers, Accelerometers, and Global Navigation Satellite System (GNSS) are heterogeneous sensor types to name a few. Heterogeneous sensors are commonly used for redundancy to enhance fault tolerance and system reliability.

Why Sensor Fusion

As different sensors capture different aspects of the environment being monitored, combining these data allows for a more comprehensive and accurate understanding of the surroundings. The result is an enhanced perception of the environment, thereby enabling more informed decision-making.

While more sensors mean more data and that is good, each sensor type has its limitations and measurement biases. Sensors also often provide ambiguous or incomplete information about the environment. Sensor fusion techniques help resolve these ambiguities by combining complementary information from different sensors. By leveraging the strengths of different sensors, fusion algorithms can fill gaps, resolve conflicts, and provide a more coherent and reliable representation of the data. By fusing data from multiple sensors in a coherent and synchronized manner, fusion algorithms enable systems to respond in real time to changing conditions or events.

In essence, sensor fusion plays a vital role in improving perception, enhancing reliability, reducing noise, increasing accuracy, handling uncertainty, enabling real-time decision-making, and optimizing resource utilization.

Fusion Types and Fusion Stages

Two important aspects of sensor fusion are: (1) what types of sensor data to be fused and (2) at what stage of processing to fuse the data. The first aspect depends on the application and the second aspect depends on the types of data being fused. For example, if stereo sensors of the same type are being used, fusing is done at the point of data generation (early fusion). If image-sensor and radar are both used for identifying an object, fusing is done at late stage of separate processing (late fusion). There are other use cases where mid-fusion is performed, say for example, when doing feature extraction based on both image-sensor and radar sensing.

Modern Day Solution Trend

While traditional digital signal processing (DSP) is still the foundation for heterogeneous sensors-based systems, it is not easy to scale and automate these real-time systems as they get more complex. In addition to advanced DSP capabilities and superior sensor-fusion capabilities, AI processing is needed for scalability, robustness, effectiveness and automation requirements of large complex systems. AI-based sensor fusion combines information at the feature level, instead of fusing all data from different individual sensors.

Cadence Tensilica Solutions for Fusion-based Systems

Cadence’s Tensilica ConnX and Vision processor IP core families and floating point DSP cores, make it easy to develop sensor fusion applications. Cadence also provides a comprehensive development environment for programming and optimizing applications targeting the Tensilica ConnX and Vision processor IP cores. This environment includes software development tools, libraries, and compiler optimizations that assist developers in achieving high performance and efficient utilization of the processor resources.

Tensilica ConnX is a family of specialized processor cores designed for high-performance signal processing, AI, and machine learning applications. The architecture of ConnX cores enables efficient parallel processing and accelerates tasks such as neural network inference, audio processing, image processing, and wireless communication. With their configurability and optimized architecture, these cores offer efficient processing capabilities, enabling developers to build power-efficient and high-performance systems for a range of applications.

The Tensilica Vision Processor is a specialized processor designed to accelerate vision and image processing tasks. With its configurability and architectural enhancements, it provides a flexible and efficient solution for developing high-performance vision processing systems across various industries, including surveillance, automotive, consumer electronics, and robotics.

Summary

Cadence offers a wide selection of DSPs ranging from compact and low power to high performance optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. To learn more about these IP cores, visit the following pages.

Vision DSPs

ConnX DSPs

FloatingPoint DSPs

Also Read:

Deep Learning for Fault Localization. Innovation in Verification

US giant swoops for British chipmaker months after Chinese sale blocked on national security grounds

Opinions on Generative AI at CadenceLIVE

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Intel Internal Foundry Model Webinar

Intel Internal Foundry Model Webinar
by Scotten Jones on 06-21-2023 at 12:00 pm
Categories: Events, Foundries, Intel Foundry, Semiconductor Services, TechInsights
15 Comments

IAO Investor Webinar Slides to post on our INTC website PDF Page 07

Intel held a webinar today to discuss their IDM2.0 internal foundry model. On the call were Dave Zinsner Executive Vice President and Chief Financial Officer and Jason Grebe Corporate Vice President and General Manager of the Corporate Planning Group.

On a humorous note, the person moderating the attendee questions sounded a lot like George Takei who played Lieutenant Sulu on the original Star Trek. Since Intel is trying to accelerate what they are doing, warp 10 mister Sulu seems appropriate.

Under Intel’s historical business model, manufacturing and technology development costs were allocated to the business units and to Intel Foundry Services (IFS). The business units and IFS sold their product and had reportable profit and loss statements (P&L). Under the new model, manufacturing, technology development, and IFS will be a reportable P&L and will sell wafers to the Intel business units at market prices, see figure 1.

Figure 1. Internal Foundry Model

This realignment will put a big focus on the new Internal Foundry Business Unit (or whatever they decide to call it). The business units will have increasing freedom to choose processes from internal and external sources and the internal unit will have to compete on price and performance. It will also make it easier to benchmark the internal manufacturing against external foundries because they will be competing on price and with a standalone P&L the relative financial performance will be clear.

The new structure will force the business units to pay a premium for hot lots the same way fabless companies do at foundries. Apparently, Intel runs a lot of hot lots, and it is impacting capacity by 8 to 10%. As a former fab manager, I can confirm that hot lots are very disruptive to fab operations, I hated them and strictly limited how many could be in the fab at one time.

Intel expects that initially operating margins will be negative and as they scale up and address their cost structure, they expect to move positive, see figure 2.

Figure 2. Manufacturing Operating Margins

Intel is delivering $3 billion dollars in cost reduction this year with $2 billion dollars in operating expense and $1 billion dollars in cost of sales savings, They are targeting $8 to $10 billion dollars in saving exiting 2025. Figure 3. Summarizes some identified savings opportunities.

Figure 3. Cost Savings Opportunities

In Q1 of next year the internal foundry business unit will have approximately $20 billion dollars of revenue making it the second largest foundry in the world. Virtually all the revenue in Q1 will be internal products but this is the same path Samsung has taken and they also have a lot of internal revenue.

I think this is an excellent realignment on Intel’s part to ensure their internal manufacturing is competitive on both a technology and cost basis.

One area in the presentation I have an issue with is the following slide, see figure 4.

Figure 4. IFS Customers Benefit from IDM Engineering

The idea behind figure 4 is that Intel will be designing and piloting four products on each new node before external customers get access to the node so Intel will have worked through the early issues and customers will get a more mature process. In my opinion this shows a lack of understanding of the foundry model on Intel’s part. Leading edge fabless companies are not going to accept being many months or even a year behind the leading edge. At TSMC leading fabless customers are involved in the definition and testing of new processes and are lead customers so they can be first to market. A company like Apple is involved and pays to be first to market, they are not going to wait for Intel to launch the processes on their own products first.

There was a discussion on process technology. The five nodes in four-year message was repeated and it was noted two of the five nodes are now done and the other three are on track. I personally don’t count i7 as it is really a plus version of 10nm, but even four nodes in four years is impressive.

Figure 5. Five Node in Four Years

Historically Intel was a leader in process technology introducing a new process every two years. The way I have always thought about Intel processes is they will have a node n in high volume production, are ramping up a new node n+1, and ramping down a previous node n-1. They typically have 3 to at most 4 nodes running at any time and this means older nodes are being regularly retired.

Figure 6. IDM 1.0 Drive Decades of Success

Slide 7. Illustrates how Intel views the changes in the market.

Slide 7. What Changed in the Environment

When I look at this slide, I agree with the left side graph, capital intensity is increasing. I don’t completely agree with the middle graph. Yes, disaggregation will likely increase node tails, but the reality is the node tails have historically been far shorter for Intel than for the foundries because Intel is focused on leading edge microprocessors. TSMC is still running their first 300mm fab on 130nm that entered production in the early 2000s, Intel’s 130nm production shut down by the late 2000s. Disaggregation will help Intel use more trailing edge technology, but external foundry customers will likely be an even larger driver of trailing edge if Intel succeeds in the foundry business.

David Zinsner specifically mentioned that running fabs past their depreciable lifetime generates cash and increases margins. This is a key part of the success of the foundry model. TSMC is still running 130nm, 90nm, 65nm, 40nm, 28nm, and 16nm fabs that are fully depreciated and are the cash cows paying for new technologies and have the highest margins. It may seem counter intuitive but the newest nodes with high depreciation pull down TSMC’s corporate margin by a couple of points of the first two years. When a fab becomes fully depreciated the wafer cost drops more than half and the foundries only pass on some of that savings to the customers increasing gross margins.

The longer node life will be particularly critical for Intel going forward, with i4 ramping, i3 coming this year, and 20A, and 18A next year, all EUV based processes, under the old 3 nodes running policy Intel’s non EUV processes would all be disappearing by 2025. As I have written about previously, Intel has a large portfolio of fabs that will never convert to EUV and they will need a use for those fabs, external customers can provide that. That article is available here.

On the right side of figure 7. Intel lines up their processes and timing versus competitors. I agree that at 32nm and 22nm Intel was well ahead and at 14nm the lead narrowed and at 10nm they fell behind. I am not sure exactly what the criteria is for the alignment of i4, i3, 20A and 18A versus the competitor processes. Certainly, from a timing perspective it is correct, but how did they decide what Intel processes match up to what foundry processes? On a density basis I would say even 20A and 18A likely won’t match TSMC 3nm but on a performance basis they will likely exceed even TSMC 2nm.

During the call Dave Zinsner said Intel expects to announce their first 18A customer this year. During questioning he was asked what is holding up the announcement and he said it is maturity of the PDK. This matches up with what Daniel Nenni has been hearing that the Intel 18A models aren’t ready yet.

In conclusion, I believe that creating a P&L around Intel Internal Foundry is a positive step to help drive competitiveness. I don’t completely agree with all aspects of the message on this call but I do think that overall Intel is making good progress and moving in the right direction.

Some people have speculated this is a step toward Intel eventually splitting the company, I am not sure I see that happening, but this would likely make that easier if it ever happened.

Intel’s execution on process technology has gotten a lot better and is in my opinion the single biggest driver of their future success. The Tower acquisition wasn’t discussed but will in my opinion also be a key piece in finding external foundry business to fill all the Intel non EUV fabs.

Also Read:

The Updated Legacy of Intel CEOs

VLSI Symposium – Intel PowerVia Technology

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

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The Updated Legacy of Intel CEOs

The Updated Legacy of Intel CEOs
by Daniel Nenni on 06-21-2023 at 10:00 am
Categories: Foundries, Intel Foundry
69 Comments

Intel HQ 2023

(First published December 24, 2014)

A list of the best and worst CEOs in 2014 was recently published. The good news is that none of our semiconductor CEOs were on the worst list. The bad news is that none of our semiconductor CEOs were on the best list either. I will be writing about the CEOs that made our industry what it is today starting with the largest and most innovative semiconductor company in the world.

Intel was officially founded in 1968 by Robert Noyce and Gordon Moore (Moore’s Law) with Andy Grove joining as employee number three. These three gentlemen would also be the first three of only eight CEOs over an unprecedented forty six year history. During their thirty year tenure at Intel, Noyce, Moore, and Grove became legends transforming Intel and the entire semiconductor industry into a force of nature that changed the world, absolutely. I would also add Intel CEO number four to that list since Craig Barrett is credited with the now famous Intel “copy exact” manufacturing process that has enabled “Moore’s Law” to continue to this day.

Here are brief bios of the first four Intel CEOs. As you can see there is a common thread amongst their education: PhDs from the top technology academic institutions across the United States.

Robert N. Noyce
Intel CEO, 1968-1975, Co-founder of Fairchild Semiconductor
Education: Ph.D in physics, Massachusetts Institute of Technology

Gordon E. Moore
Intel CEO, 1975-1987, Co-founder of Fairchild Semiconductor
Education: Ph.D in chemistry and physics, California Institute of Technology

Andrew S. Grove
Intel CEO, 1987-1998, previously worked at Fairchild Semiconductor
Education: Ph.D. in chemical engineering, University of California-Berkeley

Craig R. Barrett
Intel CEO, 1998-2005
Joined Intel in 1974, served as chief operating officer from 1993 to 1997, president from 1997 to 1998; chief executive from 1998 through 2005; and chairman from 2005 until 2009.
Education: Ph.D. in materials science, Stanford University

Without Intel where would we be today? We would certainly not have super computing power on our laps nor would we be designing SoCs with FinFETs. As a computer geek since the 1970s and a Silicon Valley based semiconductor professional since the 1980s I have a much better appreciation for Intel than most. I do however fear for their future which is why I am writing this. The problems Intel faces today in my opinion started with an MBA. Who exactly thought that putting a finance guy in charge of the most innovative semiconductor company in the world was a good idea?

Paul S. Otellini
Intel CEO, 2005-2013
Joined the Intel finance department in 1974 . From 1996 to 1998, Otellini served as executive vice president of sales and marketing and from 1994 to 1996 as senior vice president and general manager of sales and marketing.
Education: MBA, University of California-Berkeley, 1974; B.A. in economics, University of San Francisco, 1972

Paul Otellini’s legacy includes two very defining events:

  • In 2006 he oversaw the largest round of layoffs in Intel history when 10,500 (10% of the workforce) were laid-off in an effort to save $3 billion per year in costs.
  • Also in 2006 he passed on the opportunity to work with Apple on the iPhone.

“We ended up not winning it or passing on it, depending on how you want to view it. And the world would have been a lot different if we’d done it. The thing you have to remember is that this was before the iPhone was introduced and no one knew what the iPhone would do. At the end of the day, there was a chip that they were interested in that they wanted to pay a certain price for and not a nickel more and that price was below our forecasted cost. I couldn’t see it. It wasn’t one of these things you can make up on volume. And in hindsight, the forecasted cost was wrong and the volume was 100x what anyone thought.”

That was the day Intel “missed” mobile. Apple ended up partnering with TSMC which disrupted the foundry business with the half node process development methodology. This new yield learning centric strategy put TSMC solidly in the process technology lead ahead of both semiconductor industry titans Intel and Samsung.

I remember the rumors swirling Silicon Valley after Otellini’s resignation: Would Intel hire an outsider or promote from within? The potential outsider names I heard were very impressive but Intel chose Brian Krazinch, a career Intel employee with zero CEO experience. I was disappointed to say the least.

Brian M. Krzanich
Intel CEO 2013-2018
Began his career at Intel in 1982 in New Mexico as a process engineer and has progressed through a series of technical and leadership roles at Intel, most recently serving as the chief operating officer (COO) since January 2012. Prior to becoming COO, he was responsible for Fab/Sort Manufacturing from 2007-2011 and Assembly and Test from 2003 to 2007. From 2001 to 2003, he was responsible for the implementation of the 0.13-micron logic process technology across Intel’s global factory network. Krzanich also held plant and manufacturing manager roles at multiple Intel factories.
Education: BA in Chemistry from San Jose State University

In 2015-2016 Intel eliminated more than 15,000 jobs companywide which is now the largest downsizing in the company’s history.

“14nm is here, is working, and will be shipping by the end of this year” Brian Kranzich IDF 2013 Keynote. (Intel 14nm officially shipped in 2015).

Intel 14nm was the beginning of the end of Intel’s process technology dominance and at 10nm Intel hit rock bottom. Brian Kranzich was forced out as CEO of Intel for an improper relationship with a co-worker many years prior to becoming CEO. In reality BK was fired for being the worst CEO in the history of Intel, my opinion.

Robert Swan
Intel CEO January 2019-2021
Bob Swan was CEO of Intel Corporation from January 2019 until February 15, 2021. He joined Intel as CFO in October 2016 from General Atlantic,  Bob was formerly CFO at eBay, Electronic Data Systems, and TRW. Following the resignation of Brian Krzanich, he was named interim CEO on June 21, 2018, and appointed to full-time CEO on January 31, 2019. Bob was replaced by 30 year Intel employee and former VMware CEO Pat Gelsinger.
Education: Bachelor’s degree in Business Administration from the University of Buffalo, MBA from Binghamton University.

Again, no CEO experience. During Bob’s short reign Intel struck an outsourcing deal with TSMC to support a chiplet strategy which is now in production (Meteor Lake). Intel can use internal fabs or TSMC depending on which is best suited. In my opinion Bob did this as a way to motivate Intel manufacturing as an innovate or die mandate. Some think this is why Bob was fired but, as it turns out, the Intel-TSMC relationship was in fact a pivotal point in the history of Intel.

Pat Gelsinger
Intel CEO 2021-Present
Pat Gelsinger rejoined Intel as CEO on February 15, 2021. He started his career at Intel in 1979, where he spent 30 years in various roles and eventually rose to become the company’s first Chief Technology Officer (CTO). During his tenure at Intel, Gelsinger played a crucial role in the development of several groundbreaking technologies and microprocessors, including the 80486 processor and the original Pentium processor. Before returning to his “dream job” at Intel, Pat was CEO of VMware (2012-2021), a software company specializing in virtualization and cloud computing.
Education: Bachelor’s degree in Electrical Engineering from Santa Clara University, Master’s degree in Electrical Engineering from Stanford University.

Pat brought Intel back to the forefront of the semiconductor industry with the much heralded Intel IDM (Integrated Device Manufacturing) 2.0 strategy.

Intel IDM 2.0 is a plan introduced by Gelsinger to transform its manufacturing capabilities. It also represents a significant shift in Intel’s approach to manufacturing and involves a combination of strategies aimed at expanding its product portfolio, enhancing competitiveness, and increasing supply chain resilience.

The key elements of Intel IDM 2.0 include:
  1. Foundry Services: Intel plans to leverage its advanced manufacturing facilities and offer its manufacturing capabilities to external customers through Intel Foundry Services. This initiative aims to become a major player in the foundry business and provide advanced semiconductor manufacturing solutions to a diverse range of industries.
  2. Internal Product Leadership: Intel continues to prioritize its internal product development and plans to deliver a cadence of leadership products. The focus is on enhancing process technology and driving advancements in chip design to maintain Intel’s position as a leading provider of high-performance and high-efficiency semiconductor solutions.
  3. Investments in Research and Development: Intel has committed significant investments in research and development to drive innovation and accelerate advancements in semiconductor technologies. This includes investments in next-generation process nodes, packaging technologies, and specialized designs for specific market segments.
  4. Global Supply Chain Resilience: Intel aims to enhance its supply chain capabilities by diversifying its manufacturing locations and increasing capacity. This strategy is intended to improve responsiveness to market demands, mitigate potential disruptions, and ensure a reliable supply of Intel products.
  5. Partnerships and Ecosystem Collaboration: Intel recognizes the importance of collaboration and partnerships to drive industry-wide advancements. The company is actively engaging with partners, customers, and governments to foster innovation, develop new technologies, and create a robust ecosystem that supports the growth of the semiconductor industry.

Intel is a changed company with IDM 2.0 which has been covered by SemiWiki in great detail. Pat Gelsinger is a no nonsense – transformative leader with a very large challenge ahead of him. For the sake of Intel and semiconductor manufacturing let’s hope he is successful, absolutely.

Also Read:

VLSI Symposium – Intel PowerVia Technology

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Intel Foundry Services Forms Alliance to Enable National Security, Government Applications

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Managing Service Level Risk in SoC Design

Managing Service Level Risk in SoC Design
by Bernard Murphy on 06-21-2023 at 6:00 am
Categories: Arteris, IP

Traffic

Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum service level agreement (SLA). A printer display may work fine most of the time yet will intermittently corrupt the display. Or the nav system in your car intermittently fails to signal an upcoming turn until after you pass the turn. These are traffic (data) related problems. Conventional performance metrics only ensure that the system will perform as expected under ideal conditions; SLA metrics set a minimum performance expectation within specified traffic bounds. OEMs ultimately care about SLAs, not STAs. Meeting/defining an SLA is governed by interconnect design and operation.

What separates SLA from ideal performance?

Ideally, each component could operate at peak performance, but they share a common interconnect, limiting simultaneous traffic. Each component in the design has a spec for throughput and latency – perhaps initially frames/second for computer vision, AI recognition, and a DDR interface, mapping through to gigabytes/second and clock cycles or milliseconds in a spreadsheet. An architect’s goal is to compose these into system bandwidths and latencies through the interconnect, given expected use cases and the target SLA.

Different functions generally don’t need to be running as fast as possible at the same time; between use cases and the SLA, an architect can determine how much she may need to throttle bandwidths and introduce delays to ensure smooth total throughput with limited stalling. That analysis triggers tradeoffs between interconnect architecture and SLA objectives. Adding more physical paths through the interconnect may allow for faster throughput in some cases while increasing device area. Ultimately the architect settles on a compromise defining a deliverable SLA – a baseline to support a minimum service level while staying within PPA goals. This step is a necessary precursor but not sufficient to define an SLA; that step still needs to factor in potential traffic.

Planning for unpredictable traffic

Why not run simulations with realistic use cases? You will certainly do that for other reasons, but ultimately, such simulations will barely scratch the surface of SLA testing across an infinite range of possibilities. More useful is to run SystemC simulations of the interconnect with synthetic initiators and targets. These don’t need to be realistic traffic models for the application, just good enough to mimic challenging loads. According to Andy Nightingale (VP of product marketing at Arteris), you then turn all the dials up to some agreed level and run. The goal is to understand and tune how the network performs when heavily loaded.

An SLA will define incoming and outgoing traffic through minimum and maximum rates, also allowing for streams which may burst above maximum limits for short periods. The SLA will typically distinguish different classes of service, with different expectations for bandwidth-sensitive and latency-sensitive traffic. Between in-house experience in the capabilities of the endpoint IP together with simulations the architect should be able to center an optimum topology for the interconnect.

The next step is to support dynamic adaptation to traffic demands. In a NoC, like FlexNoC from Arteris, both the network interface units (NIUs) connecting endpoint IPs and the switches in the interconnect are programmable, allowing arbitration to dynamically adjust to serve varying demands. A higher-priority packet might be pushed ahead of a lower-priority packet or routed through a different path if the topology allows for that option, or a path might be reserved exclusively for a certain class of traffic. Other techniques are also possible, for example, adding pressure or sharing a link to selectively allow high priority low-latency packets to move through the system faster.

It is impossible to design to guarantee continued high performance under excessive or burst traffic, say, a relentless stream of video demands. To handle such cases, the architect can add regulators to gate demand, allowing other functions to continue to operate in parallel at some acceptable level (again, defined by the SLA).

In summary, while timing closure for ideal performance is still important, OEMs care about SLAs. Meeting those expectations must be controlled through interconnect design and programming. Arteris and their customers have been refining the necessary Quality of Service (QoS) capabilities offered in their FlexNoC product line for many years. You can learn more HERE.

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DDR5 Design Approach with Clocked Receivers

DDR5 Design Approach with Clocked Receivers
by Daniel Payne on 06-20-2023 at 10:00 am
Categories: EDA, Siemens EDA

DFE min

At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5 specification came out in 2020 with a data transfer bandwidth of 3200MT/s, requiring equalization (EQ) circuits to account for the channel impairments.

DFE is designed to overcome the effects of Inter-Symbol Interference (ISI), and the designers at Micron had to consider the clocking, Rx eye evaluation, Bit Error Rate (BER) and jitter analysis in their DRAM DFE. IBIS-AMI models were used to model the DDR5 behavior along with an EDA tool statistical simulation flow.

Part of the DDR5 specification is the four-tap DFE inside the DRAM’s Rx, and the DFE looks at past received bits to remove any ISI from the bits. The DFE first applies a voltage offset to remove ISI, then the slicer quantizes the current bit as high or low.

Typical 4-tap DFE from DDR5 Specification

With DDR5 the clocking is a differential strobe signal (DQS_t, DQS_c), and it’s forwarded along the single-ended data signals (DQ) to the Rx. The DQS signal is buffered up and then fanned out to the clock input of up to eight DQ latches, causing a clock tree delay.

DQS Clock tree delay

The maximum Eye Height is 95mV and the max Eye Width is 0.25 Unit Interval (UI), or just 78.125ps.. Using a statistical approach to measuring BER of 1e-16 is most practical.

IBIS models have been used for many generations of DDR systems, enabling  end-to-end system simulation, yet starting with DDR5 adding EQ features and  BER eye mask requirements, a new simulation model and analysis are sought. With IBIS-AMI modeling there is fast and accurate Si simulation that are portable across EDA tools while protecting the IP of the IO details. IBIS-AMI supports statistical and bit-by-bit simulation modes, and the statistical flow is shown below.

Statistical Simulation Flow

The result of this flow is a statistical eye digram that can be used to measure eye contours at different BER levels.

DDR5 Example Simulation

A DDR5 simulation was modeled in the HyperLynx LineSim tool, with the DQ and DQS IBIS-AMI models provided by Micron, and here’s the system schematic.

DDR5 system schematic

The EDA tool captures the waveform at specified clock times, where timing uncertainties within clock times are transferred into the resulting output eye diagram, reconstructing the voltage and timing margins before quantization by the slicer and its clock.

Variable clock times

Both DQS and and DQ timing uncertainty impact the eye diagram similar to timing margin. Figure A shows jitter injected onto the DQ signal, and figure B has jitter injected onto the DQS signal. DQ (red) and DQS (green) jitter are shown together in figure C.

Timing bathtub curve

Sinusoidal jitter effects can even be modeled on the DQ signal and DQS signal in various combinations to see the BER and timing bathtub curve results. DDR5 has Rj, Dj and Tj measurements instead of period and cycle to cycle jitter measurements. The impact of Rx and Rj values on the BER plots can be simulated, along with the timing bathtub curves.

Rx Rj on data, versus data and clock combined

Going beyond Linear and Time-Invariant (LTI) modeling, the Multiple Edge Response (MER) technique uses a set of rising and falling edges. With a custom advanced IBIS-AMI flow it performs a statistical analysis on each MER edge, then superimposes the combined effect into an output eye diagram.

Bit-by-bit, advanced simulation results

Adding Tx Rj values of 2% in the modeling shows even more realistic degraded BER plot results.

Summary

Signal Integrity effects dominate the design of a DDR5 system, so to get accurate results require detailed modeling of all the new physical effects. The IBS-AMI specification has been updated for Rx AMI models to use a forwarded clock. Micron showed how they used a clocked DDR5 simulation flow to model the new effects, including non-LTI effects, and achieving simulations with BER of 1e-16 and below.

Request and read the complete 25 page white paper online here.

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Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint
by Kalar Rajendiran on 06-20-2023 at 6:00 am
Categories: EDA, Foundries, IP, Samsung Foundry, Synopsys

Synopsys Samsung silicon wafer

Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments such as high performance computing (HPC), mobile, client computing, and automotive electronics. The compute demand on systems has also been growing at unbelievable rates every couple of years. The tremendous growth in artificial intelligence (AI) driven systems and advances in deep learning neural network models have certainly contributed to this and pulled us into the “SysMoore Era.” And multi-die systems are becoming essential to address the system demands of the SysMoore Era.

Given the above trends, silicon IP is going to play an even more critical role in the future growth of the semiconductor market. Yesterday’s off-the-shelf IP is not going to cut it when it comes to specific PPA requirements of various applications. It is all about differentiated IP for specific applications and processes. In the SysMoore Era, IP development strategy should be driven not only by looking forward to the next node  but also looking at vertical market requirements, horizontally (process variants) and backwards as multi-die systems enable the optimization of process technologies.

Last week, Synopsys announced an expanded agreement with Samsung Foundry to develop a broad portfolio of IP to reduce design risk and accelerate silicon success for automotive, mobile, and HPC markets, and multi-die designs as well. I had an opportunity to chat with John Koeter, senior vice president of product management and strategy for IP at Synopsys. My discussion focused on understanding how this agreement is different and the important role the supported market segments and multi-die systems trend played in arriving at an expanded agreement. Following is a synthesis of my discussion, highlighting the salient points.

Proactive Collaboration by Looking at Vertical Market Needs

Synopsys and Samsung Foundry have a long history of collaborating when it comes to IP development. Generally speaking, IP development in the past was driven by specific mutual customer demand. Given the compressed time-to-market demand of the SysMoore Era, customers cannot afford to wait for long development cycles after specific IP requests. IP development needs to start proactively based on anticipating future vertical market. And that is what Synopsys and Samsung Foundry are doing per this expanded agreement. They will analyze market segments and develop the needed IP to holistically address vertical market needs. For example, together they will consider what a next-generation ADAS chip or a next-generation MCU or next generation mobile chip will look like and proactively develop IP to address those needs. IP will also be optimized according to the end application needs. For instance, PCIe IP for the HPC market will be optimized for minimum possible latency whereas PCIe IP for the automotive market will be optimized for reliability over a wider temperature range.

For the automotive market in specific, Synopsys will optimize IP for Samsung’s 8LPU, SF5A and SF4A automotive process nodes to meet stringent Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements. The auto-grade IP for ADAS SoCs will include design failure mode and effect analysis (DFMEA) reports that can save months of development effort for automotive SoC applications.

Anticipating Multi-die Systems Requirements

As monolithic chip implementations give way to multi-die system implementations, it is no longer about just the next advanced process node. A multi-die system could have various dies in different process nodes and still deliver the performance and power requirements at a reduced cost compared to a monolithic implementation. This opens up the opportunity to consider creating advanced IP (say PCIe Gen6) for older process nodes to support I/O chiplets of a multi-die system. Synopsys and Samsung are proactively considering such opportunities and will develop a portfolio of advanced IP on many process nodes as well as collaborating on developing high-speed UCIe IP for chip-to-chip communication.

Agreement Expansion Leading to Increase of IP Footprint

As a result of the above identified IP collaboration strategies, the availability IP for Samsung Foundry processes is going to increase significantly. For customers, that is a significant uptick in terms of access to IP in the age of post-Covid era when clear supply chains are high up on their requirements list. With this agreement, Synopsys IP available or in development for Samsung processes includes logic libraries, embedded memories, TCAMs, GPIOs, eUSB2, USB 2.0/3.0/3.1/4.0, USB-C/DisplayPort, PCI Express 3.0/4.0/5.0/6.0, 112G Ethernet, Multi-Protocol 16G/32G PHYs, UCIe, HDMI 2.1, LPDDR5X/5/4X/4, DDR5/4/3, SD3.0/eMMC 5.1, MIPI C/D PHY, and MIPI M-PHY G4/G5.

Synopsys’ Certified Design Flows Accelerate Time to Silicon Success

A broad portfolio of IP from a single vendor has multiple advantages, in both business and engineering terms. From an engineering perspective, for example, power grid or pin location misalignments when integrating various IP blocks are going to be less likely. Synopsys is also working very closely with Samsung on the EDA side to develop and certify various reference flows which should help accelerate time to silicon success.

To read the full press release, click here. For more information, contact Synopsys.

Also Read:

Requirements for Multi-Die System Success

An Automated Method to Ensure Designs Are Failure-Proof in the Field

Automotive IP Certification

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Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023
by Daniel Nenni on 06-19-2023 at 10:00 am
Categories: Ansys, Inc., Chiplet, EDA, Events, Foundries, Samsung Foundry

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As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering the opening keynote for this year’s SAFE Forum on June 28th at 10:15 a.m. in San Jose, California.

Ansys is the world leader in both system and electronic multiphysics simulation and analysis, with a strong reputation in the semiconductor market for the reliability and accuracy of its Ansys RedHawk-SC family of power integrity signoff products. Ajei’s keynote, “The 3Ps of 3D-IC,” draws from the company’s unique market position that encompasses chip, package, and board design. Leading semiconductor product designers have adopted 2.5D and 3D-IC packaging technologies that allow multiple, heterogeneous silicon die to be assembled or stacked in a small form-factor package. This provides huge advantages in performance, cost, and flexibility — but heightens analysis and design challenges, including thermal analysis, electromagnetic coupling, and mechanical stress/warpage. Samsung Foundry has been on the forefront of enabling 3D-IC with manufacturing innovations and design reference flows that include best-of-breed solutions like those offered by Ansys.

Learn how to Clear 3D-IC Hurdles

Ajei will present an executive perspective of the challenges facing multi-die chip and system designers. Ansys is a multibillion-dollar company with a deep technology background in an array of physics, from chip power integrity to thermal integrity, mechanical, fluidics, photonics, electromagnetics, acoustics, and many more. This broad portfolio gives Ansys a unique perspective of how 3D-IC technology is compressing traditional chip, package, and board design into a single, new, interlinked optimization challenge.

Ajei will explain how this new reality creates three sets of hurdles for chip design teams that threaten to slow the broader adoption of 3D-IC technology by the mainstream IC market. In response to these challenges, Ajei will present his “3Ps,”: which suggest a program of thoughtful solutions for how the design community can tackle these obstacles and move 3D-IC design toward widespread adoption.

One of the 3Ps stands for partnerships, which are key to Ansys’ successful collaboration with Samsung Foundry. It is clear to any experienced observer of the EDA market that the complexity of today’s design challenges have grown beyond the ability of any one company to solve. This is just as true for semiconductor design tools as it is for the semiconductor manufacturing equipment industry.  – No one vendor delivers all the equipment used in a fab, and no one software vendor can meet all design tool requirements. The way forward is to engage deeply with ecosystem initiatives like SAFE and ensure that customers have access to the best-in-class tools for every step of their design process.

Register for the Samsung Foundry Forum and SAFE Forum and join Ansys in fostering industry collaborations and partnerships to improve the capabilities of the semiconductor industry. Visit the Ansys booth at the SAFE exhibit (June 28 @ Signia by Hilton, San Jose, CA) to speak with EDA experts on 3D-IC design techniques and requirements.

Also Read:

WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC design technology

Chiplet Q&A with John Lee of Ansys

Multiphysics Analysis from Chip to System

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Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing
by Fred Chen on 06-19-2023 at 6:00 am
Categories: Lithography

Brightfield (red) and darkfield (purple) sidelobes in 84 nm

Current 1a-DRAM and 5/4nm foundry nodes have minimum pitches in the 28 nm pitch range. The actual 28 nm pitch patterns are one-dimensional active area fins (for both DRAM and foundry) as well as one-dimensional lower metal lines (in the case of foundry). One can imagine that, for a two-dimensional routing pattern, both horizontal and vertical lines would be present, not only at 28 nm minimum pitch, but also larger pitches, for example, 56 or 84 nm (2x or 3x minimum pitch, respectively). What are the patterning options for this case?

0.33 NA EUV

Current 0.33 NA EUV systems are unable to simultaneously image both horizontal and vertical 28 nm line pitch, as they each require incompatible illumination dipole illuminations (Figure 1). Hence, two exposures (at least) would be needed for a two-dimensional layout. In fact, even unidirectional 28 nm pitch could require double patterning [1].

Figure 1. Vertical lines require the X-dipole (blue) exclusively while the horizontal lines require the Y-dipole (orange) exclusively.
High-NA EUV

Planned high-NA (0.55 NA) EUV systems can image both horizontal and vertical 28 nm pitch lines simultaneously, but runs into a different problem for the 56 nm and 84 nm pitches. When the dipole illumination targets the 28 nm anchor pitch, the central obscuration removes the first diffraction order for the 56 nm pitch. The 56 nm pitch case essentially becomes the 28 nm pitch. Thus, it would have to be exposed separately with different illumination. The central obscuration also removes the first and second diffraction orders for the 84 nm pitch, causing sidelobes to appear in the intensity profile [2]. The sidelobes are valleys for the brightfield case, and peaks for the darkfield case (Figure 2).

Figure 2. Brightfield (red) and darkfield (purple) sidelobes in 84 nm pitch for 28 nm pitch dipole illumination with 0.55 NA. The first and second diffraction orders have been removed by the central obscuration of the pupil.

These sidelobes lead to random photon numbers crossing the printing threshold around the sidelobe locations, leading to stochastic defects (Figures 3 and 4).

Figure 3. 40 mJ/cm2 absorbed dose, 84 nm pitch, brightfield case. The dark spots in the orange space indicate locations of stochastic defects corresponding to the sidelobe valleys in Figure 2.

Figure 4. 40 mJ/cm2 absorbed dose, 84 nm pitch, darkfield case. The narrow orange lines are the result of sidelobe printing, corresponding to the sidelobe peaks in Figure 2.

Figure 4. 40 mJ/cm2 absorbed dose, 84 nm pitch, darkfield case. The narrow orange lines are the result of sidelobe printing, corresponding to the sidelobe peaks in Figure 2.

DUV immersion lithography with SAQP and selective cuts

Surprisingly, the more robust method would involve DUV lithography, when used with self-aligned quadruple patterning (SAQP) and two selective cuts [3]. This scheme, shown in Figure 5, builds on a grid-based layout scheme developed by C. Kodama et al. at Toshiba (now Kioxia) [4].

Figure 5. Flow for forming a 2D routing pattern by SAQP with two selective cuts. One cut selectively etches the covered green areas (1st spacer), while the other selectively etches the covered purple areas (core/gap). The etched areas are refilled with hardmask (dark blue). The final pattern (orange) is made by etching both the remaining green and purple areas.

Figure 5. Flow for forming a 2D routing pattern by SAQP with two selective cuts. One cut selectively etches the covered green areas (1st spacer), while the other selectively etches the covered purple areas (core/gap). The etched areas are refilled with hardmask (dark blue). The final pattern (orange) is made by etching both the remaining green and purple areas.

Of course, where available, EUV self-aligned double patterning (SADP) may also be used as an alternative to DUV SAQP, but the two selective etch exposures will still be additionally needed. While SAQP has an extra iteration of spacer (or other self-aligned) double patterning over SADP, this extra complexity is much less than the staggering infrastructure difference between EUV and DUV. Conceivably, players without EUV are still able to continue to produce chips with two-dimensional interconnecting patterns, at least down to ~25-26 nm pitch.

References

[1] D. De Simone et al., Proc. SPIE 11609, 116090Q (2021).

[2] F. Chen, Printing of Stochastic Sidelobe Peaks and Valleys in High NA EUV Lithography, https://www.youtube.com/watch?v=sb46abCx5ZY, 2023.

[3] F. Chen, Etch Pitch Doubling Requirement for Cut-Friendly Track Metal Layouts: Escaping Lithography Wavelength Dependence, https://www.linkedin.com/pulse/etch-pitch-doubling-requirement-cut-friendly-track-metal-chen/,2022.

[4] T. Ihara et al., DATE 2016.

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing 

Also Read:

A Primer on EUV Lithography

SPIE 2023 – imec Preparing for High-NA EUV

Curvilinear Mask Patterning for Maximizing Lithography Capability

Reality Checks for High-NA EUV for 1.x nm Nodes

Podcast EP168: The Extreme View of Meeting Signal Integrity Challenges at Wild River Technology with Al Neves

Podcast EP168: The Extreme View of Meeting Signal Integrity Challenges at Wild River Technology with Al Neves
by Daniel Nenni on 06-16-2023 at 10:00 am

Dan is joined by Al Neves, Founder and Chief Technology Officer at Wild River Technology. Al has 30 years of experience in design and application development for semiconductor products and capital equipment focused on jitter and signal integrity. He is involved with the signal integrity community as a consultant, high-speed system-level design manager and engineer.

Dan explores signal integrity challenges of high performance design with Al. Wild River’s unique combination of process, products and skills are explained by Al, along with the motivation for the company’s approach to addressing signal integrity. It turns out success demands an all-or-nothing approach across the entire design and development process.  The best partner is an organization with the expertise and attitude to win, no matter what it takes.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Requirements for Multi-Die System Success

Requirements for Multi-Die System Success
by Daniel Nenni on 06-16-2023 at 6:00 am
Categories: Chiplet, EDA, Synopsys

Synopsys Chiplet Report 2023

Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.

As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about. Hundreds of thousands of people around the world have read our chiplet coverage making it the #1 trending topic on SemiWiki for 2023 and I expect this to continue into 2024, absolutely.

In fact, Synopsys just released an industry insight report titled “How Quickly Will Multi-Die Systems Change Semiconductor Design?” that is well worth the read. The report also includes insights on multi-die systems from Ansys, Arm, Bosch, Google, Intel, and Samsung. Additionally, Synopsys CEO Aart de Geus wrote the opening chapter:

“As angstrom-sized transistors intersect with multi-die Si-substrates, we see classic Moore pass the baton to SysMoore,” writes de Geus. “Today, Synopsys tracks more than 100 multi-die system designs. Be it through hardware / software digital twins, multi-die connectivity IP, or AI-driven chip design, we collaborate closely with the leading SysMoore companies of tomorrow.”

Here is the report introduction:

For many decades, semiconductor design and implementation has been focused on monolithic, ever-larger and more complex single-chip implementation. This system-on-chip approach is now changing for a variety of reasons. The new frontier utilizes many chips assembled in new ways to deliver the required form-factor and performance.

Multi-die systems are paving the way for new types of semiconductor devices that fuel new products and new user experiences.

This Synopsys Industry Insight brings together a select group of keystone companies who are advancing multi-die systems. You’ll read the thoughts of senior executives from various levels of the technology stack. You’ll also hear from Synopsys’ CEO, its president and a panel of Synopsys technology experts. We’ll discuss our achievements, what lies ahead and how we are partnering with the industry to drive change.

Synopsys also recently completed an excellent webinar series on the topic which is well worth your time. You can watch this On-Demand HERE.

Synopsys Chiplet Webinar Series abstract:

The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design, secure and robust die-to-die connectivity, reliability and health, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful.

Topics include:
  • Multi-Die System Trends, Challenges and Requirements
  • Benefits of Early Architecture Design for Multi-Die Systems
  • Innovations in Multi-Die System Co-Design and System Analysis
  • Successful Connectivity of Heterogeneous Dies with UCIe IP
  • Identifying and Overcoming Multi-Die System Verification Challenges
  • Optimizing Multi-Die System Health from Die to Package to In-Field

Bottom line: Chiplets are a disruptive technology driving the semiconductor design ecosystem without a doubt. If you want to explore chiplets in greater detail Synopsys would be a great start.

Also read:

Chiplet Interconnect Challenges and Standards

Chiplet Q&A with Henry Sheng of Synopsys

Chiplet Q&A with John Lee of Ansys

Multi-Die Systems: The Biggest Disruption in Computing for Years