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Analog Circuit Migration and Optimization

Analog Circuit Migration and Optimization
by Daniel Payne on 07-18-2023 at 6:00 am
Categories: EDA, MunEDA

WiCkeD Flow, analog circuit optimization

The MunEDA User Group Meeting (MUGM)  has been an annual event since 2006, and this year there were some 80 participants from many customers that attended to share their experiences and learn how to get the best EDA tool results. I’ve been able to view the presentations and archived videos, so will share some of the interesting successes in specific tool categories.

There were two presentations from engineers at ST Microelectronics on how they performed analog circuit migration and optimization with the help of design automation software. Caroline Vaganay from ST Microelectronics works in their PDK and Design Flows group, and she compared the WiCkeD tool from MunEDA for analog circuit migration versus another vendor across three internal designs.

Their criteria in comparing EDA tools for analog circuit migration were:

  • Specification-driven circuit optimization
  • Pre-defined corners, statistical corners
  • SPICE simulators supported
  • Design migration and exploration
  • Accuracy – confidence, local minima, feasibility
  • Run times
  • Usability
  • Pricing
  • Support

Three circuits were used in their benchmarks:

  • OPAMP
  • Voltage Reference
  • Bandgap

The general design flow for the WiCkeD tool is shown below:

For the OPAMP circuit designed at 0.25um they wanted to look for better trade-off options by improving Vio and Icc across all PVT corners, achieving a PGB > 20 MHz. Optimization results showed that all performance values were within specs at nominal and worst case corners, and the runtime was only 4h 5min to complete 7,455 simulations. The performance robustness improved and the total yield improved from 14% to 71% at worst case conditions.

Their second circuit to optimize was a Voltage Reference Buffer using 40nm technology, with objectives to improve current recopy across PVT corners to minimize any process variation impacts. WiCkeD was directed to change design parameters to reduce the local variation, resulting in standard deviation improvements on performance metrics:

  • DELTA_PC_X10 lower, 46%
  • DELTA_PC_X10 upper, 44%
  • DELTA_PC_X8, lower, 38%
  • DELTA_PC_X8, upper, 45.7%

Caroline’s final benchmark circuit was a Bandgap reference in 0.18um, with objectives to optimize the resistor network to get  a minimum compensated curvature over the full temperature range, while showing stability and reaching PSRR, consumption and bandwidth goals.

The WiCkeD  optimizer was able to meet all performance goals and DC conditions in just 8,107 simulations, taking 9h 40min of simulation time. With MunEDA tools they beat other tools by speed and accuracy, finding solutions when others couldn’t.

Schematic Porting Tool – SPT

Maxime Blattes from ST Microelectronics shared his evaluation of SPT, and their steps used to port a schematic were:

  • Store parameters from the source schematic
  • Find the corresponding devices in a mapping table
  • Apply a translation and rotation to the new instance
  • Reconnect the wire on the new pins
  • Apply parameters to new instances with scaling
  • Run update parameters procedure

Their previous flow with Cadence Virtuoso required customization that was difficult for non-CAD engineers, and required a Skill developer. The promise of a porting tool was in saving time and talent. SPT is a GUI-based tool, making it easier for engineers to use quickly for tasks like symbol mapping, property mapping, and automatically extracting a schematic. The longest part of porting before was solving the wire updating issue, now automated with SPT.

Designers that are not CAD engineers can use SPT on their own, create any needed templates quickly, and learning the tool in a short time. What took them just 30 minutes using SPT required about 2 days before using SKILL coding.

A third presentation by Matthias Sylvester of MunEDA was a demo of SPT where he ported an example schematic from 180nm to 90nm of a 3 pin to 3 pin MOS design, then a 3 pin to 4 pin MOS. His main points about SPT for schematic porting were:

  • SPT remembers to recalculate all properties
  • Uses your hierarchy
  • Ports between all process nodes and fabs
  • SPT can stretch the new schematic as needed
  • Connectivity is checked before and after porting
  • SPT was more powerful and convenient than other tools
MunEDA SPT

Summary

Analog circuit migration and optimization can be either a manual or automated process, and the WiCkeD tool from MunEDA has been used for 15 years at companies like ST Microelectronics to automate the process, producing results that are meeting specifications like area, yield, performance and robustness. Yes, analog design is still part art and part engineering, but using EDA automation tools gives your engineers better results in less time than manual methods. The Schematic Porting Tool – SPT, is a fast way to migrate any schematic between nodes and fabs.

Visit MunEDA at the 60th DAC, booth 1407 in Moscone West, July 10-12th.

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Calibre’s next move – Correct-by-Construction IC Layout Optimization

Calibre’s next move – Correct-by-Construction IC Layout Optimization
by Peter Bennet on 07-17-2023 at 10:00 am
Categories: EDA, Siemens EDA

DesignEnhancer

Siemens EDA’s next move in its Calibre shift left strategy is the addition of correct-by-construction IC layout optimization for the most critical emerging physical design challenges. Calibre’s new DesignEnhancer product supports both custom and digital ICs and is already in use by several leading IC design companies. It targets three problem areas: optimization of vias, power grids and faster, higher quality decoupling capacitor and filler cell insertion.

But why get a signoff and verification tool involved in implementation and how is this better than the current P&R flow solutions ?

The principle’s nothing new – Calibre’s always had some design fixing capabilities. And it’s already tightly integrated with all leading layout flows.

But the critical reason is that layout tools aren’t always that good at some of the tasks they’ve traditionally been asked to do. Whether that’s slowness in the case of filler insertion or lack of precision in what they do – since they don’t have signoff quality rule-checking – meaning either later rework or increased design margining.

This matters on today’s highly complex designs and advanced process technologies. Users noticed the costs in design cycle time, quality and performance and pushed Siemens to make the Calibre capabilities available earlier in the flow where these were superior.

Via and Power Grid Optimization – Calibre DesignEnhancer Via & Pge

The importance of via resistance in leading edge processes makes more precise via implementation important. Designers need a more accurate picture of both timing and IR drop from the initial routing step. Leaving it any later means potential over-design for timing closure and late rework for IR drop and EM issues.

But that’s not possible without signoff quality DRC decks and rule checking. Hence Calibre’s new DesignEnhancer Via that supports both signal and power grid and via optimization by integrating Calibre into the layout flow both immediately after routing and with integrated incremental optimization after design ECO routes.

Siemens show a typical via optimization from DesignEnhancer Via below:

The improved version on the right clearly has more vias.

But the optimization isn’t limited to that – we also want to use the best possible vias (and perhaps in some local cases this means fewer). Layout tools can’t always make the best decisions here and may compromise. Calibre’s signoff quality DRC means that DesignEnhancer Via can do this. And that translates to more precise timing and reduced IR drop (particularly on SoC designs) as shown below:

No one wants to get through to design signoff and find late EM and IR drop problems that a better power grid and power routing might have avoided much earlier in the flow. DesignEnhancer Pge (Power Grid Enhancer) provides optimization of already Calibre clean power routing for both interconnect wiring and vias so that a more precise power grid can be used from much earlier in the implementation flow.

This example shows the potential for inserting further power routing and reducing IR drop.

Again, results can show dramatic reductions in IR drop.

Better Filler and Decap insertion run time and quality – DesignEnhancer Pvr

Inserting filler, decap and ECO cells has long been a painfully slow part of the P&R flow. But Calibre has always been able to insert these cells far more quickly and with more precise user control. Design Enhancer Pvr now shifts that capability back into those P&R flows.

Of course, none of that’s any real help if it doesn’t run any faster. Which it does – an order of magnitude faster – and that’s the full round-trip time from the layout tool DB:

Summary

Today’s increasingly complex design and process technologies are exposing gaps in the implementation design flow. Siemens is showing some real creativity in their shift-left strategy. What’s unique about the new Calibre DesignEnhancer product is the addition of automated, analysis-aware, Calibre correct-by-construction layout optimization at an earlier stage in the flow where it makes a real difference in reducing IR drop.

Customers already have results to prove this really does cut through to reduced design cycle time and better design quality. Design kits are available for the major foundries and supported for all major layout design flows (both custom and digital), which already have tight and efficient Calibre integration, making user adoption straightforward.

Siemens state their mission for Calibre is to make chip design to tapeout as fast and easy as possible for its customers – so it’s against that standard this product should be judged.

Expect to see more information from Siemens EDA following this product launch.

Calibre DesignEnhancer

Also Read:

The Siemens Digital Industries Software View of AI and its Impact on System Design

Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform

Transforming the electronics ecosystem with the component digital thread

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The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am
Categories: Agnisys, EDA

Figure 3

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath all this, the real world is analog, and the fundamental effects of electricity and silicon can’t be ignored or abstracted away.

One of these inconvenient truths is metastability, which can occur wherever a signal crosses between flip-flops on asynchronous clocks, called a clock domain crossing (CDC). If the input to the receiving flip-flop changes too close to its active clock edge, the flip-flop can take an indeterminate value before settling to a one or zero. If the flip-flop feeds the indeterminate value to downstream logic, the circuit may produce incorrect results.

Since there’s no way to avoid metastability, best practices for CDC design require that the downstream logic receives only valid values. The classic way to ensure this is to use a synchronizer consisting of two flip-flops on the receiving clock. If properly designed, there is a very high probability that the signal will have settled before it is clocked into the second flip-flop. Thus, only valid values are passed on to the rest of the circuit.

Multi-bit signals such as data buses require another approach since the bits may have different delays and an incorrect data value may be loaded into the receiving flip-flops. The best way to handle this is a handshake synchronizer, which creates a multi-cycle path (MCP) for the data bits so the inputs to the receiving flip-flops will be stable by the time the values are clocked in. This ensures that there is no metastability.

One common location for CDCs is the control and status registers (CSRs) used by low-level software to control and monitor chip hardware. CSR blocks have a software interface from which programs running on host systems (such as device drivers) or code running on the chip’s own embedded processors can write or read the registers. The software interface and register blocks themselves are usually in the system bus clock domain.

CSR blocks also have a hardware interface from which the rest of the chip can read or write the registers. The hardware uses this interface to read configuration values, communicate status back to the software, handshake with the software, and exchange data. Since the rest of the chip is almost always on a different clock than the system bus, there is a CDC that must be handled properly. Typically, two handshake synchronizers are used, one for the write path and one for the read.

Agnisys provides a pushbutton solution for clock domain crossings related to register blocks. Our IDesignSpec™ Suite helps chip architects and engineers create an executable specification for CSRs and automatically generate outputs for software and hardware teams. This includes generating the RTL code for the register block (in VHDL, Verilog, SystemVerilog, or SystemC) plus a bus slave and decode logic specific to the system bus protocol (AHB, APB, AXI, TileLink, or proprietary).

If the registers are in a different clock domain than the system bus, our solution also generates RTL for all the synchronization logic plus assertions for use in formal CDC verification. We support all three types of synchronizers discussed plus other options, including two-level flip-flops, mux, handshake, async FIFO synchronizers, and custom synchronizer blocks. We also handle cases in which the register block is in its own separate clock domain, distinct from the system bus and the rest of the hardware design.

We have many users who have benefitted from this automation. They do not need to worry about CDCs at all: they simply tell us their preferred synchronizer style and we generate everything for them. We have a lot of experience with CDCs and synchronization, and we are sharing our expertise with the rest of the industry. We are actively participating in the new Clock Domain Crossing Working Group within the Accellera Systems Initiative, focused on creating a standard for CDC abstraction models.

Should you want to have a discussion about clock domain crossing or any other design challenges, or would like to see a demo of the latest enhancements to our IDesignSpec Suite please contact us directly.

Agnisys is here to help you accelerate your IP/SoC front-end development with the industry’s leading Golden Executable Specification Solutions.

WEBINAR: An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Also Read:

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

ISO 26262: Feeling Safe in Your Self-Driving Car

DAC 2021 – What’s Up with Agnisys and Spec-driven IC Development

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SEMICON West 2023 Summary – No recovery in sight – Next Year?

SEMICON West 2023 Summary – No recovery in sight – Next Year?
by Robert Maire on 07-15-2023 at 6:00 am
Categories: AI, Events, Semiconductor Advisors, Semiconductor Services
2 Comments

Semicon west 2023

-SEMICON well attended but bouncing along the biz bottom
-Recovery seems at least a year away with memory even more
-AI creates hope but not impactful- Disconnect tween stocks & reality
-AMAT me too platform- Back end benefits from chiplets

SEMICON busy but subdued

SEMICON is certainly back to pre-covid levels or perhaps better. The show has turned its focus primarily to smaller tool makers or sub suppliers with larger companies having no floor presence and only doing private meetings in hotels. In general the show is a bit sparse but still a great place to network.

The general tone was positive for the long term but subdued and negative for the near term as we continue to bounce along the bottom in the current down cycle with no particular detectable change in momentum over the last 6 months or more.

Recovery at least a year away, likely longer for memory

This down cycle feels a lot like the downturn of 2000 which was fairly long lived. We see a similar pattern of over capacity that was brought about by the YTK buildup and in the current case the post Covid build up.

As we have also seen in the past, so called industry analysts always seem to suggest the downturn will be short lived and we will see a recovery in 6 months. Then six months comes around with no recovery and they kick the can down the road for another six months, saying the recovery is just another 6 months away.

Our view from the beginning of this downturn is that this downturn is fundamentally different , more systemic and therefore longer. It appears we have been correct so far in our more pessimistic projections.

We are already over a year in the current downturn which makes it one of the longer down cycles, at least as compared to more recent cycles.

We think that given current macro economic outlook coupled with semiconductor industry demand/capacity balance that we are at least a year off from a recovery.

The recent down month for TSMC revenues is certainly not a very good trend.

Memory will certainly take longer to recover as the supply demand imbalance is far worse than foundry or logic.

HBM is only bright spot in memory but far from enough

High bandwidth memory is the only bright spot in an otherwise ugly supply/demand imbalance. HBM is being driven by the AI craze which is clearly fantastic but is way to small overall to make up for the vast majority of memory applications which remain very weak.

Memory makers will certainly do everything to reallocate production to HBM which could eventually swamp demand and reduce premium pricing but at the very least it will help the acceleration of AI which will be good for the rest of the chip industry.

Fab project delays likely to increase as downcycle stretches

In short cycles of the past, new fab projects continue without much delay as by the time the building shell is done the industry is already in a recovery and equipment move in coincides with an upturn which works out.

The combination of a longer downcycle and a more tepid recovery will likely delay the many anticipated fab projects. Even though it seems like we continue to hear new projects every week, its almost a certainty that not all of them will ever get built let alone built on time.

TSMC is clearly having issues in Arizona. Intel is at least a year and probably a lot more delayed in Ohio.

Yet we still hear of new projects in Europe, Israel, Japan etc;. What we could eventually see is that given the likely over supply, chip makers will pick and choose to continue fab projects in countries and areas that offer the best economics and delay/cancel those that are not as attractive

What will Intel choose when faced with its current excess capacity situation with fabs planned for Arizona, Ohio, Europe & Israel? There is no way that all are going to be built….especially on time….it would be throwing gasoline on an already raging bonfire.

Memory is in far worse oversupply, with excess inventory, reduced production and loss making pricing. Some memory makers , such as Micron , would have a hard time even affording a fab project until we are firmly into an upturn. For memory that could be into 2025 with Boise not starting to come on line until 2027 and beyond and Clay NY years behind that probably into 2030’s.

Delays will require re-work of CHIPS for America

We have previously said that the CHIPS Act needs a “re-work”. The downcycle clearly was just way unlucky timing but it means that many of these now delayed fab projects will fall well outside of the 5 year time window originally scoped out for CHIPS.

If you are Micron, you are likely past the intended CHIPS Act window with most projects.

Getting enough HR talent for the chip industry is obviously a larger problem than first thought. Materials such as rare earth elements that we have been warning about for several years are now turning into the problem we anticipated as they became a weapon.

We wonder when CHIPS act money will have to be re-allocated to insure supply of critical rare earth element refining capacity which is non existent in the US.

In short circumstances have radically changed since the CHIPS act was envisioned and we need to quickly adjust or risk wasting money and time.

We still don’t have any plans for back end and packaging as all the lime light has been focused on front end fabs.

No big announcements at SEMICON – Only a “me too” platform from AMAT

There were no significant technology announcements at SEMICON and the only product announcement was AMAT with a “platform” change that goes to a “linear” configuration rather than a circular configuration for tool chambers

This is pretty much a “me too” announcement that follows in the foot steps of Lam’s “Sense.I” platform, announced a long while ago, to reduce footprint by going both linear and vertical.

Many manufacturers have been down this road as a linear configuration allows higher density versus circular “”mainframe” based designs that were more about accommodating the wafer handling robots. AMEC in China has long had a linear design along with an ill fated etch tool from Intevac or the “slingshot” from Semitool over a decade ago…..nothing new here.

BESI back end beneficiary of 3D packaging

The one significant thing, which is not particularly new, is the increased focus on packaging due to “more than Moore”, Chiplets and 3D packaging etc;.

Die & wafer bonding, die stacking and attach, interposer technologies and all things related to packaging multiple die are clearly very hot and in great demand.

BESI, has been in the packaging business forever and has worked very hard in relative obscurity in the little recognized dark recesses of chip making that was previously taken for granted. Obscure no more….Now they are working with the likes of AMAT that want to focus on the newly important back end of the industry where BESI has great technology and a long rich history. It has ben 27 years since we worked on the IPO of a little Dutch company that is finally in the spotlight…….

Disconnect between semiconductor reality and stock prices continues

Semiconductor stocks remain hot for no good reason whatsoever. We poke to a number of industry executives who privately commented that the disconnect was crazy and were fearful of a correction.

While we certainly agree with all the hype of AI and perhaps even more so than some of the optimistic bull cases….we think AI could be way bigger than the internet.

The disconnect is that while this is all great for the semiconductor industry it is not the be all, end all, that is the sole driver of chips that many people assume. Much as with the internet revolution, the supporting semiconductor infrastructure is critical to its functioning but sooner or later becomes a bit more mundane as telecommunications devices have become over time.

The chip stocks are acting like AI is going to double chip demand and launch the industry out of its current downcycle neither of which will likely happen.

AI is great for chips but not the savior that a global macroeconomic recovery would be.

The stocks

While SEMICON West seems back to its old self, the performance of the industry is far from it yet the stocks are acting as if it were…..

What to do?

Buy into the thundering herd mentality or risk being left in the dust.

Perhaps the real answer is to be increasingly selective and not just buy into a random sampling of chip stocks.

Looking for laggards or beaten down names that have yet to recover and lightening up on those that have been overheated.

We would want to be more defensive, perhaps a bit more biased to the small cap side.

Right now, the tidal wave that is AI is raising every boat in chips to new heights but sooner or later investors will be more selective.

Our concern is that as realization of a longer downturn comes about, investors patience may get tested and they may look for greener pastures while waiting on a recovery that is taking longer.

Time waits for no one.

Also Read:

SEMICON West 2023 Summary – No recovery in sight – Next Year?

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory

Podcast EP172: RISC-V International, Today and Tomorrow with Calista Redmond

Podcast EP172: RISC-V International, Today and Tomorrow with Calista Redmond
by Daniel Nenni on 07-14-2023 at 10:00 am

Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry.

Dan explores the momentum RISC-V International has achieved in the market with Calista. Current developments to facilitate the standard are discussed, along with the impact of key strategic relationships. Calista reviews the organization’s significant presence at DAC, as well as substantial events elsewhere around the world.

Calista clarifies the question of whether RISC-V is open source or an open standard. She also discusses what lies ahead.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: Rob Gwynne of QPT

CEO Interview: Rob Gwynne of QPT
by Daniel Nenni on 07-14-2023 at 6:00 am
Categories: CEO Interviews

Rob Gwynne

I am joined today by Rob Gwynne, Founder and CEO of QPT. He is a genuine polymath as his technical experience spans digital, analogue, mixed signal and RF electronics, EMC, radar, DSP, FPGA, software development (embedded, drivers, application level), advanced PCB layout and simulation, optics, precision instrumentation, motion control, power systems and plasma physics!

Rob, I read on your website that you are going to change the world of electric motors for the better and help the planet. How are you going to do that?

Cutting the use of fossil fuels is vital to fight climate change. We are a clean tech company dedicated to improving electrical efficiency. We have focused on electrical motors as they consume 45% of the world’s energy according to the International Energy Agency (Energy-Efficiency Policy Opportunities for Electric Motor-Driven Systems). The trouble is that, rather like a car engine is tuned for efficiency in the middle speed range being an average of usage conditions, motor drives are also fine-tuned. However, this sweet spot is at maximum load and electric motor VFD (Variable Frequency Drive) manufacturers quote circa 97% efficiency. The efficiency actually drops off by up to 50% as the load decreases so, in real world condition where the load can vary considerably, there is a lot of power being wasted because the motor drive is not operating efficiently.

So, it is rather like the difference between the fuel consumption of a car running at a steady 50 MPH which is optimal for the engine and a car running a real world, urban cycle of different speeds and starts and stops?

Exactly. It is never questioned that 97% efficiency figure does not apply in lower load conditions. Not only have we found that it drops significantly but we have also found and patented a solution. Excitingly this enables electric motor drives to deliver 99.5% efficiency at full load range but, more importantly, the efficiency at lower loads is significantly higher than any current solutions.

That could have a phenomenal effect in reducing power usage if widely adopted. Why has this not been investigated before and what are the causes of the inefficiencies?

The controls for electric motors have hardly changed for many years. If you believe that you have achieved 97% efficiency, why would power engineers waste time and money trying to improve near perfection?

The inefficacies arise when the voltage is chopped to create the changing in frequency that is used to drive the motor. This is called a Variable Frequency Drive (VFD). Traditionally, normal silicon or Silicon Carbide (SiC) transistors are used but these are slow to switch resulting in high, switching energy losses.

The key to the losses is that Si and SiC transistors have body diodes that need to be charged and discharged on every switching cycle of the power converter, wasting energy on every cycle which is why there is low efficiency of these converters at low output power. Try and drive them faster and these losses become greater.  This, together with the switching loss due to slow switching, forces engineers using Si and SiC transistors to run the converters at low frequency as the charging/discharging losses become unacceptable at higher frequencies.

People have tried to use Gallium Nitride (GaN) transistors at MHz switching speeds compared to the usual 10-100 KHz to try and create smaller, more efficient and reliable drives. But, at these much higher frequencies, RF emissions become a problem and the designs would not pass EMI compliance testing unless you throttle back the speed which negates the benefits of using GaN.

So how do you solve that?

That’s where my broad skill set comes into play. Power engineers are focused on being an expert in one field and have developed skills and design approaches that work at 10-100Khz switching which is where Si and SiC transistors operate. However, I was also able to look at the problem as an RF engineer and create a solution that enables the GaN transistors to be run at their full potential of up 20 MHz with nanosecond switching with no heat or EMI issues.

As a result, our VFD module enables motors to be driven at up to 99.7% efficiency at peak load and to save significant power at lower loads compared to existing solutions. In real world operating conditions with variable loads, we estimated that this could provide savings in power consumption of 10% or more compared to current products. This comes from the faster switching speeds of GaN transistors and that they do not have the body diodes inherent in Si and SiC transistors that are a major energy loss as they charge and discharge.

I have done a number of videos that go into all the different aspects of this technology that are available on the website www.q-p-t.com

Do you have products?

Yes, we have modules available for evaluation. They form a drop-in replacement for existing 20 KW motor control modules. These are used in so many industries such as heat pumps, industrial motors and electric vehicles. Widespread adoption of our technology by them could significantly reduce energy costs and CO2 production and its impact on climate change. This will be helped by there not being any significant difference in the cost of using our technology over the existing, plus we provide up to 10% reduction in energy running costs! I passionately believe that this is an effective way to reduce climate change.

Also Read:

Defacto Celebrates 20th Anniversary @ DAC 2023!

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

CEO Interview: Dr. Sean Wei of Easy-Logic

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400 GbE SmartNIC IP sets up FPGA-based traffic management

400 GbE SmartNIC IP sets up FPGA-based traffic management
by Don Dingee on 07-13-2023 at 10:00 am
Categories: Achronix, eFPGA
2 Comments

Achronix ANIC

Sustaining wire-speed 400 GbE transfers is only a first step in managing enterprise traffic. Adding rules-based filtering to sift packets in real time can stress most networking hardware to a breaking point, slowing down an entire network. Architects are trying to spread these loads, distributing intelligent traffic management away from high-end firewalls and other appliances toward endpoints where traffic originates – but 400 GbE hardware with an integrated rules engine hasn’t scaled down easily. Achronix has a solution building on its Speedster7t FPGA integrating a 400 GbE packet interface, PCIe Gen 5, a flow processor with a rules engine, and room left for customer logic to differentiate 400 GbE SmartNIC designs.

All the pieces needed for a 400 GbE SmartNIC in one FPGA

Transceivers capable of 400 GbE are popping up on more than one high-end FPGA. But the problem of creating suitable “plumbing” in an FPGA for 400 GbE is often left as an exercise for the reader. Two projects within Achronix, with help from its acquisition of Accolade IP and expertise in September 2022, have thought through the entire IP chain and are coming together for a complete solution under the Achronix Network Infrastructure Code (ANIC) banner.

“We don’t think anyone has 400 GbE with this type of flow processing and rules engine for an endpoint right now,” says Scott Schweitzer, CISSP, Director of SmartNIC Product Planning at Achronix. It starts with enabling technology – the ANIC Shell, an Ethernet packet-flow pipeline in RTL. This project dates back to 100 GbE and PCIe Gen 3 technology, concentrating on FIFOs, parsing, and DMA elements needed to keep packets moving smoothly. In a Speedster 7t, over half of the logic remains available for customers.

 

 

Next came moving from the shell to the complete ANIC for a 400 GbE SmartNIC with the flow processor and rules engine, still with around 50% of the Speedster7t logic left.

 

 

Bumping ANIC up to 400 GbE might look easy from this diagram, but Schweitzer points out two points in the chain needing specific attention. “To get to a host at 400 Gb, we needed every bit of PCIe performance we could get – 16 lanes of PCIe 5 keeps the DMA engine fed,” says Schweitzer. “We also needed faster memory for the DMA and FIFO, and four channels of GDDR6 on each side got us there.

Visualized in the Speedster7t footprint, the ANIC looks like this. Note these are all optimized IP blocks with verified closed timing at speed.

 

Opening new possibilities for intelligent traffic management

ANIC forms a foundation for SmartNIC development, allowing customers to define packet shaping and traffic management capabilities in endpoint-scale hardware running at 400 GbE SmartNIC speeds. Customers gain faster time-to-market and control over customization of the ANIC IP and their value-add logic. Duplicating or de-duplicating packets, running local key-value stores, and other operations are possible on packet streams using SmartNICs.

Network security improves with intelligent traffic management for both receive and transmit, but SmartNICs have traditionally applied policies only on  receive. ANIC enables policies to be applied to both received and transmitted data. “Let’s say one night, there’s an application server suddenly generating unusual volumes of traffic at 2 am when nobody should be working,” Schweitzer begins an anecdote. “In a conventional enterprise networking architecture, the increased traffic would reach an appliance like a high-performance firewall, and it would have to have the proper rules to stop the packets. By moving those same rules out to a 400 GbE SmartNIC with ANIC IP installed in the application server, the suspicious traffic never leaves it, preventing propagation and reducing the load on the network.”

Artificial intelligence (AI) also looms large on the scale of ANIC possibilities. Machine learning processors (MLPs) in the Speedster7t could learn and deploy ANIC rules by observing SmartNIC traffic patterns before network security teams notice a vulnerability. Endpoint-native learning could also drive a virtual, distributed, intelligent load balancer, offloading traffic to other platforms if concentrated traffic patterns emerge.

Achronix is putting a solid effort into ensuring its high-performance Speedster7t FPGA is ready for advanced real-world applications. A 400 GbE SmartNIC is just one possible use case for the Speedster7t – and it’s a good one since few other approaches can achieve the same results. We’d expect customer innovation to take over with a range of differentiated solutions built on 400 GbE ANIC IP.

Learn more in the Achronix press release:
Achronix Pushes the Boundaries of Networking with 400 GbE and PCIe Gen 5.0 for SmartNICs

Also Read:

eFPGA Enabled Chiplets!

The Rise of the Chiplet

Achronix on Platform Selection for AI at the Edge

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The Siemens Digital Industries Software View of AI and its Impact on System Design

The Siemens Digital Industries Software View of AI and its Impact on System Design
by Mike Gianfagna on 07-13-2023 at 6:00 am
Categories: AI, EDA, Siemens EDA

The Siemens Digital Industries Software View of AI and its Impact on System Design

The impact of AI seems to be everywhere. Products are smarter, doing more of what used to be done by the humans. Complex tasks can be completed quicker and with greater accuracy and failures can now be predicted more reliably and repaired before they even occur. The AI technologies used to make all this happen and how those technologies are applied to tasks familiar to SemiWiki readers is the subject of a new white paper from Siemens Digital Industries Software. The white paper presents a comprehensive view of our changing world; this is required reading for those doing electronic system design. A link is coming, but first let’s examine the Siemens Digital Industries view of AI and its impact on system design.

The AI Tools of the Trade

The term AI, or artificial intelligence has a very broad meaning. It represents a collection of algorithms and information processing strategies. Many of these concepts have been around for quite a while, some dating back to the 1940’s. A combination of new application strategies enabled by vast processing power has created the revolution we are witnessing now. According to the white paper:

During the last ten years, artificial intelligence (AI) has progressed from a visionary concept to a mainstream reality in many large companies.

The white paper provides a very useful overview of the technologies at play in this revolution and how they fit together to address real-world problems. I recommend you get the first-hand view of all this from the white paper. These technologies are woven together using mathematics, computer science, statistics, and psychology. They include machine learning and deep learning. The goals of AI application discussed are broad and include:

  • Make informed decisions, increasing efficiency
  • Complete routine tasks with minimal effort, improving productivity
  • Improve expertise by recommending next tasks

AI Applied to PCB Design

PCB design is used as an example in the white paper to illustrate the impact of AI. PCB design challenges engineers to generate designs that have adequate power and cooling for complex and fast ICs while maintaining signal and thermal integrity for every high-speed signal between the various ICs on a board. The complexity of the problem can explode quickly. This application provides a great backdrop to see the various ways AI can revolutionize design. 

Many aspects of AI’s impact on the design process are discussed in the white paper. Here is a brief summary to whet your appetite:

Learning curve: Experienced engineers develop an intuition about how to optimally apply tools and set options. This is the main reason the productivity of a senior engineer is so much higher than that of a junior engineer. What if AI could capture this intuition, allowing junior engineers to perform like senior engineers?

Component selection: Engineers spend a lot of time researching the selection of components to optimally address system requirements. What if a model could be developed based on historical information to cut this problem down substantially?

Component model creation: Generating models to represent the components (e.g., symbols, 2D/3D physical geometries, and simulation models) takes a lot of time and demands many different skillsets. What if natural language processing, image recognition, and ML could be applied here?

Schematic connectivity: Optimal component placement and connection requires a broad perspective of the design. Here is another opportunity for AI assistance.

Dynamic reuse: The knowledge applied to one design is often lost once the design is completed. What if institutional knowledge could be saved and curated?

Constraints: Again, prior knowledge can make this task much easier with higher quality results.

Layout: These tasks use heuristics to optimally automate the process. What if AI can target those heuristics to be more specific and more accurate?

Analysis and verification: Design sensitivity to factors such as material properties, physical layout and temperature/voltage all conspire to make this process challenging. What if AI can refine the interdependencies to a more predictable model?

Design synthesis: Pulling it all together, generative AI approaches can have a big impact.

The Big Picture

Siemens Digital Industries Software has a very broad footprint. Its customers span many markets, industries and applications. The white paper discusses some of the investments being made to deploy AI across this broad footprint.

Examples discussed include:

  • AI/ ML-based accelerators for edge applications get to market faster
  • Genetic algorithm-based optimization to build an efficient decoupling capacitor set for a power delivery network
  • An adaptive UI to improve user productivity by predicting the commands that users will most likely want to use
  • Delivery of 90 percent accuracy on next-step suggestions in microflows
Siemens Xcelerator portfolio

This is an incredibly broad set of AI applications across design, manufacturing, and production. As part of the Siemens Xcelerator portfolio, these tools help electronic systems design companies leverage AI technologies to deliver futuristic products to market today.

To Learn More

Here is a link to the new white paper, Reducing Electronic Systems Design Complexity with AI. AI will change the face of design and manufacturing. I highly recommend you download this white paper to learn more. It will help you to understand the Siemens Digital Industries view of AI and its impact on system design.

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Transforming RF design with curated EDA experiences

Transforming RF design with curated EDA experiences
by Don Dingee on 07-12-2023 at 10:00 am
Categories: EDA, Keysight EDA

How to Design an RF Power Amplifier course screenshot

Access to sophisticated RF EDA tools is one thing. Effectively harnessing their capability in real-world use is another. Digital EDA and test & measurement providers have long recognized ongoing customer education needs for their solutions. Keysight is embarking on an initiative to develop curated EDA experiences with a wide range of free learning for RF EDA solutions.

Curation brings users better information

Keysight teams already produce a massive quantity of information online, most of which lives a very long life somewhere tied to an asset. “If you go and search Keysight.com for ‘oscilloscopes’ today, you’re going to come up with thousands of documents, videos, applications, notes, and white papers,” says Linas Dauksa, Senior Digital Marketing Manager for Keysight. “Much of this material we’ve developed as vendor-neutral for learning to do something with any oscilloscope – we’re teaching users, not selling gear.”

Still, an unaided search can produce many results – some new, some old, some on target, some not maintained. Curation can pull better results to the top, but it takes skilled resources. For the last four years, Keysight has quietly assembled an experienced digital learning team to begin the process, creating a portal called Keysight University as a first step and collecting RF EDA content in pages like this one focused on RF circuit designers.

 

 

 

 

 

 

 

 

 

 

 

 

 

“We originally thought of Keysight University as a pre-sales tool,” says Julie Pildner, Digital Learning Marketing Manager. “Soon, we discovered people were using the information in many different ways at all points in their journey – and the journey didn’t necessarily take them through the portal for everything they found useful.”

Formatting for smoother consumption in short or long form

A funny thing happens when asking people to pay for anything: expectations jump. There’s always a freemium model, where introductory information is openly available, and higher-value content is behind a paid subscription wall. The hope is free material demonstrates enough value to convince a user to subscribe and get more access for a fee. That approach can leave a lot of users behind, however.

“If I’ve paid for a subscription, and I launch into a 45-minute webinar without well-designed sections, there’s a risk I lose interest before I get the information I was looking for,” says Richard Duvall, RF EDA Portfolio Marketing Manager. “To solve that, we’re converting many of our longer content hits into easier-to-find, easier-to-navigate lessons.”

Rather than locking the entire content behind a paywall, a user journey might take them directly to a lesson section and deliver the curated EDA experiences with minimal time and no fees invested. Duvall and others have been busy converting webinars on various topics into lesson modules that look more like this one on How to Design an RF Power Amplifier. Note how users can go hands-on with downloadable workspaces reinforcing lessons.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pildner quickly points out that learners sometimes look for full-length, deep-dive webinar content on a complex topic – or maybe long-form insight, like a boot camp, from a particular expert. She sees free Keysight content in both formats moving forward, saying, “We want to be the trusted source, the first place people think of for test and measurement and RF EDA ideas.”

Learning via curated EDA experiences sets a new tone

Starting in August, Keysight learning teams plan on moving away from the hierarchical portal and toward a smoother experience integrated with search, where users can guide their journey faster from more places in Keysight.com and other environments.

These curated EDA experiences with user access to Keysight experts are a big part of the digital transformation in enterprise RF EDA solutions. Users can see how Keysight approaches real-world RF design challenges with broader access to experts and their ideas.

To support your continuous learning effort, visit the extensive EDA course library covering RF Circuit Design, RF System Design, High-Speed Digital Circuit Design, and Device Modeling and Characterization on Keysight University.

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Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US

Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US
by Bernard Murphy on 07-12-2023 at 6:00 am
Categories: Aion Silicon, Automotive, Semiconductor Services

Sondrel scaling

It’s no secret that system companies are driving a lot of new silicon. Google, AWS, Tesla and others have well-established design teams delivering differentiated servers, AI engines and other technologies. I’m sure NVIDIA suspects sub rosa projects are already underway in many of these hyperscalers to design out their GPUs.

Below those dizzy heights, there is plenty of demand among midlevel system suppliers to build the essential brick-and-mortar silicon underlying modern electronic systems. Advances in edge AI, automotive networking and support for zonal architectures, and fixed wireless access devices for industrial and building automation are all very active domains. System builders here must also differentiate in their silicon platform to meet affordability and low-power objectives but span a spectrum from zero chip expertise, to logic design only, to an in-principle full design team not yet proven on a high-risk project.

Sondrel, a UK ASIC design services company, has provided an answer for many years to such clients, growing to be the biggest digital Design and Supply and ASIC design services organization in Europe.

About Sondrel

The company was established in the UK in 2002. Starting in back-end design services where demand is commonly highest, they have grown steadily, acquiring the ST Morocco design center and the Imagination Technologies IMG Works team, the latter adding architectural and front-end design expertise. Sondrel now has design centers in the UK, India and Morocco, with sales offices in Europe, the US and Israel (Redtree Solutions).

These are not simple designs. Even in the midrange, systems builders want video interfaces, machine learning, automotive compliance, networking, AR/VR, low-power IoT and even blockchain expertise. Design sizes are significant, one recently reported at 500 sq mils with over 30 billion transistors. They are also regularly pushing leading-edge technologies with large chip designs on 7nm and 5nm. Markets served include AI at the edge, automotive, 8K video, smart homes and cities, wearables and consumer devices.

Even more interesting, Sondrel offers a full turnkey service, from concept to delivered packaged and tested parts. They have established relationships with the principal EDA and IP suppliers, foundry relationships with TSMC, Samsung and GlobalFoundries and with leading Test and OSAT companies. Naturally, they provide supply chain management throughout this cycle. Ian Walsh (VP of Biz Dev and VP of North America Operations) makes the point that TSMC and others will only work directly with extremely high-volume customers. The only way anyone but the giants can get access to their technologies is through accredited ASIC services like Sondrel. Sondrel calls their full-service solution Design and Supply, which starts at the design concept and extends to supply chain management and delivery, distinguishing them from other lesser ASIC offerings.

Ian also adds that another key strength is their design team which has worked on over 100 designs over the last 20 years and is tightly integrated. They operate not so differently from established teams in a big semiconductor house, working on platforms they already understand (more on that next). There is plenty of opportunity to keep pushing frontiers, yet with lots of accumulated experience in managing risk. An intriguing option for a wide range of design and supply needs.

The Sondrel SFA platform

Sondrel starts with well-proven reference designs. The SFA 200 reference is architected for single-channel video and data processing, targeted at fixed and mobile (battery-powered) applications, such as Smart Home, Smart Metering, Sensor Fusion and other applications where a compact chip can provide local intelligence for end-point data processing. The SFA 250A variant adds ISO 26262 compliance, including an independent functional safety island as a basis for ASIL D compliance if requested.

The SFA 300 reference has four CPU clusters enabling powerful, scalable signal and data processing SoCs to be created faster at lower costs. This is targeted at signal and data processing applications such as 8K video, facial recognition for surveillance, smart factories, blockchain servers and medical data analysis. In a similar way, the SFA 350A reference is extended to support automotive applications.

The SFA 100 platform is designed for small-footprint IoT applications supporting features such as voice activation, image classification, gesture recognition, filtering, inference and tracking.

I think this is interesting. Turnkey ASIC Design and Supply service, load-balancing the business across the mid-tier of system companies with options to serve monster projects without overbalancing the revenue mix. You can learn more HERE.