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Overview
3D finite element method (FEM) and 3D planar method of moments (MoM) have become a standard design practice for ensuring the accuracy of the overall network simulation. However, without proper setup and use of electromagnetic (EM) analysis tools to define the structure and RF excitation (ports), designers can experience
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LIVE WEBINAR | 25 AUGUST 2021 | 11:00 AM EDT
Getting the most out of your simulation analysis results
Each time an FE model is solved, it can help create a vast amount of results data. The ability to process the data and quickly gain an understanding of the model behavior is important for a fast analysis turnaround.
The postprocessor
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Creating a final design is a sequence of operations from register-transfer-level (RTL) synthesis, through implementation to signoff. Each of these operations is further split into different steps, such as placement, clock tree synthesis, and routing. When run as part of a typical design flow, these steps generate
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Variation analysis continues to be increasingly important as process technology moves to more advanced nodes. It comes as no surprise that tool development in this area has been vigorous and aggressive. New higher reliability IC applications, larger memory sizes and much higher production volumes require sophisticated yield… Read More
There are 3 common misconceptions about debugging FPGA with the real hardware:
[LIST=1]
Debugging happens because the engineers are incompetent.
FPGA debugging on hardware ‘wastes’ resources.
A single methodology should solve ALL the problems.
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After knowing about the challenges involved in validating multicore systems and domains of system and application level tracing as explained by Don Dingee in his article “Tracing methods to multicore gladness” which is based on the first part of Mentor Embedded multicore whitepaper series, it’s time to take a deeper insight … Read More
Earlier this month I blogged about Power Management Policies for Android Devices, so this blog is part two in the series and delves into the details of using ESL-level tools for simulation and analysis. The motivation behind all of this is to optimize a power management system during the early design phase, instead of waiting until… Read More
I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More
There’s a French EDA company named DOCEA Powerthat is uniquely focused on power analysis at the ESL level and I had a chance to interview Ridha Hamza to get new insight on ESL design challenges and their approach. Ridha started out doing SRAM design at STMicroelectornics in the 1990’s, moved into the emerging field … Read More
