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Concerned about IP security threats for your SoCs?

Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip

PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

Thermal-induced Reliability Challenges and Solutions for Advanced IC Design

Choose the Right ASIC Manufacturing Model for Your Business

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

REPLAY: The Brave New World of Customized Memory

REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning

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February 20, 2018

Free Webinar on Standard Cell Statistical Characterization

Free Webinar on Standard Cell Statistical Characterization
by Tom Simon on 02-20-2018 at 12:00 pm
Categories: EDA, Events, FinFET, Silvaco
1 Comment

Variation analysis continues to be increasingly important as process technology moves to more advanced nodes. It comes as no surprise that tool development in this area has been vigorous and aggressive. New higher reliability IC applications, larger memory sizes and much higher production volumes require sophisticated yield… Read More

December 4, 2017

What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am
Categories: EDA, FPGA

Image Removed

There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

Debugging happens because the engineers are incompetent.

FPGA debugging on hardware ‘wastes’ resources.

A single methodology should solve ALL the problems.

January 22, 2015

Tracing Insight into Advanced Multicore Systems

Tracing Insight into Advanced Multicore Systems
by Pawan Fangaria on 01-22-2015 at 7:00 am
Categories: EDA

After knowing about the challenges involved in validating multicore systems and domains of system and application level tracing as explained by Don Dingee in his article “Tracing methods to multicore gladness” which is based on the first part of Mentor Embedded multicore whitepaper series, it’s time to take a deeper insight … Read More

November 18, 2014

Simulation and Analysis of Power and Thermal Management Policies

Simulation and Analysis of Power and Thermal Management Policies
by Daniel Payne on 11-18-2014 at 10:00 pm
Categories: EDA

Earlier this month I blogged about Power Management Policies for Android Devices, so this blog is part two in the series and delves into the details of using ESL-level tools for simulation and analysis. The motivation behind all of this is to optimize a power management system during the early design phase, instead of waiting until… Read More

October 10, 2014

Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am
Categories: EDA

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More

March 7, 2014

Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations

Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations
by Daniel Payne on 03-07-2014 at 6:00 pm
Categories: EDA

There’s a French EDA company named DOCEA Powerthat is uniquely focused on power analysis at the ESL level and I had a chance to interview Ridha Hamza to get new insight on ESL design challenges and their approach. Ridha started out doing SRAM design at STMicroelectornics in the 1990’s, moved into the emerging field … Read More

July 10, 2013June 14, 2019

Analysis of HLS Results Made Easier

Analysis of HLS Results Made Easier
by Randy Smith on 07-10-2013 at 4:30 pm
Categories: EDA

Image RemovedIn a recent article I discussed how easy it was to debug SystemC source code as shown in a video published on YouTube by Forte Design Systems. I also commented on the usefulness of the well-produced Forte video series. Today, I am reviewing another video in that series on analyzing high-level synthesis (HLS) results.… Read More

June 19, 2013June 14, 2019

IC Variability Analysis at DAC

IC Variability Analysis at DAC
by Daniel Payne on 06-19-2013 at 12:42 pm
Categories: EDA, Events

There were a handful of EDA vendors at DAC this year touting tools for IC variability analysis. On Tuesday I met with Firas Mohamed, CEO and President of Infiniscale.

Image Removed… Read More

October 19, 2011June 14, 2019

Apache on the Road

Apache on the Road
by Paul McLellan on 10-19-2011 at 2:01 pm
Categories: ANSYS, Inc., EDA

Image RemovedThere are lots of places that Apache is going to popping up in the next few weeks.

Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about “Chip-Package-System convergence: bridging multiple… Read More

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Tag: analysis

Free Webinar on Standard Cell Statistical Characterization

What are you ready to mobilize for FPGA debug?

Tracing Insight into Advanced Multicore Systems

Simulation and Analysis of Power and Thermal Management Policies

Full-Chip Electromigration Analysis

Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations

Analysis of HLS Results Made Easier

IC Variability Analysis at DAC

Apache on the Road

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