Free Webinar on Standard Cell Statistical Characterization

Free Webinar on Standard Cell Statistical Characterization
by Tom Simon on 02-20-2018 at 12:00 pm

Variation analysis continues to be increasingly important as process technology moves to more advanced nodes. It comes as no surprise that tool development in this area has been vigorous and aggressive. New higher reliability IC applications, larger memory sizes and much higher production volumes require sophisticated yield… Read More


What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am

There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

  • Debugging happens because the engineers are incompetent.
  • FPGA debugging on hardware ‘wastes’ resources.
  • A single methodology should solve ALL the problems.
  • Read More

    Tracing Insight into Advanced Multicore Systems

    Tracing Insight into Advanced Multicore Systems
    by Pawan Fangaria on 01-22-2015 at 7:00 am

    After knowing about the challenges involved in validating multicore systems and domains of system and application level tracing as explained by Don Dingee in his article “Tracing methods to multicore gladness” which is based on the first part of Mentor Embedded multicore whitepaper series, it’s time to take a deeper insight … Read More


    Simulation and Analysis of Power and Thermal Management Policies

    Simulation and Analysis of Power and Thermal Management Policies
    by Daniel Payne on 11-18-2014 at 10:00 pm

    Earlier this month I blogged about Power Management Policies for Android Devices, so this blog is part two in the series and delves into the details of using ESL-level tools for simulation and analysis. The motivation behind all of this is to optimize a power management system during the early design phase, instead of waiting until… Read More


    Full-Chip Electromigration Analysis

    Full-Chip Electromigration Analysis
    by Daniel Payne on 10-10-2014 at 7:00 am

    I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More


    Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations

    Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations
    by Daniel Payne on 03-07-2014 at 6:00 pm

    There’s a French EDA company named DOCEA Powerthat is uniquely focused on power analysis at the ESL level and I had a chance to interview Ridha Hamza to get new insight on ESL design challenges and their approach. Ridha started out doing SRAM design at STMicroelectornics in the 1990’s, moved into the emerging field … Read More


    Analysis of HLS Results Made Easier

    Analysis of HLS Results Made Easier
    by Randy Smith on 07-10-2013 at 4:30 pm

    In a recent article I discussed how easy it was to debug SystemC source code as shown in a video published on YouTube by Forte Design Systems. I also commented on the usefulness of the well-produced Forte video series. Today, I am reviewing another video in that series on analyzing high-level synthesis (HLS) results.

    Cynthesizer… Read More


    Apache on the Road

    Apache on the Road
    by Paul McLellan on 10-19-2011 at 2:01 pm

    There are lots of places that Apache is going to popping up in the next few weeks.

    Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about “Chip-Package-System convergence: bridging multiple disciplings… Read More