Q: What’s new this year at Infiniscale?
We announced ICLys last year, many evaluations started by semi companies. STMicroelectronics two weeks ago made an announcement using our tool.
Q: Who is using your EDA tools?
Users – Analog RF and memory designs. 32nm 28nm and 20nm FD SOI.
US Customers – asking foundries to support Infiniscale for variability.
PDK independent approach.
LETI – Biggest research and lab group for R&D, using ICLys.
US evaluations in progress.
Q: Do you support FinFET technology?
FinFETS – not focused on variability, but the tools are PDK independent and technology independent.
Input – SPICE models are the only input required.
Q: What are your specific EDA tools?
ICLysis – analyzes: Fast Monte Carlo Analsys (input is # of runs wanted, but results in fewer runs (similar claim as Solido). Works with any SPICE simulator. How to compare with brute force MC? Training takes 30 minutes, evaluation up to one month. Simulator independent.
High Sigma Analysis – memory designers want this capability, even std cell. Detect fails that are outside of spec in the tail, or even estimate the yield (tool focus), up to 200 billion simulation estimation. the techniques are different than what is used in Fast MC analysis.
Local variability analysis – Identify hotspots versus local sensitiviy. Maybe 8 parameters per deivce, times 1,000’s of devices, uses a few simulations (100’s), shows most sensitive devices. More efficient than traditional sensitivity analysis, and we can do 100’s of simulations.
True Corner Extraction – True statistical corner extractor for PVT corners, more efficient than brute force 100’s of corners, give me fewer corners. Based on the fast mc approach.
Similar claims to Solido.
Q: What should I expect in the next 12 months?
In the next year: new features to be added, new major customers, growing our team.
Closed a new contract yesterday (licenses). Time-based licenses, # of licenses.
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