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Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine how much more important EM analysis is today on chips using 20 nm and smaller geometries, with 10+ metal layers, and even 3D stacking. Valeriy Sukharev, Ph.D. of Mentor Graphics just wrote an 8 page White Paper titled: Electromigration Analysis At Advanced Nodes, so I read it today to learn what the new EM challenges are all about.

Sukharev earned his master’s degree in solid state electronics and a Ph.D. in physical chemistry of solids and interfaces. He’s been a principal engineer at Mentor since 2008, and before that was at Ponte Solutions as a chief scientist.

The power and ground nets in an IC are prone to EM effects because current flows only in one direction, and the interconnect of either aluminum or copper are subject to EM because the materials have high self-diffusivity. As current flows in a net there is atom depletion and accumulation caused by EM, creating voids and hillocks respectively:

Void and hillock formation

Using a Tunneling Electron Microscope (TEM), researchers at E. Zshech of Fraunhofer IZFP-D showed what voids look like:

Can two identical metal lines with the same electrical load have different EM characteristics? Yes, because there is variation in grain boundaries and atomic diffusivities. The Time To Failure (TTF) is a distribution function, so here’s a chart showing electrical resistance change as a function of time:

Effect of voiding on line resistance

Ideal equations for EM behavior are well understood and come from James Black and Blech calculated some 50 years ago. These equations don’t take into account new effects, like:

  • Dependency of MTTF on residual stress
  • Across-die variation
  • Layout dependent variables

Sukharev is proposing a new physics-based MTTF compact model, which does take into account the new effects listed above. This new model takes into account:

  • Temperature and current density effects
  • Impact of residual stress
  • Process variation

As an example, consider the following table where the time to create a void (the void nucleation time) inside of a 100um length line is a function of the current density and temperature of the stressing test. Values in yellow are immortal, meaning they will not have EM failure. The left column (J/test) has the conditioning temperature responsible for thermal stress-induced voiding.

Expect the next generation of EM tools to take into account a more optimistic approach that more closely model the actual physics of corner current densities and temperatures in the presence of variations. Residual stress effects will also be included in EM calculations for more accurate predictions. Read the complete White Paper here, after a brief registration process.

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