The impact of AI seems to be everywhere. Products are smarter, doing more of what used to be done by the humans. Complex tasks can be completed quicker and with greater accuracy and failures can now be predicted more reliably and repaired before they even occur. The AI technologies used to make all this happen and how those technologies… Read More
Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:
This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More
eSilicon recently released a paper detailing its experiences and its thoughts on the future of chiplets. The author of the white paper is Dr. Carlos Macián. I have also covered a presentation given by Carlos recently at the AI Hardware Summit, and he is well-spoken and quite knowledgeable. To get the white paper, go to the eSilicon… Read More
We have all seen the announcements to provide ever-increasing network capabilities within the data centers. Enabling these advances are improvements in connectivity including SerDes, PAM4, optical solutions, and many others. It seems 40G is old news now, and the current push is for 400G – things are changing very quickly.… Read More
Functional safety (FuSa) is a big deal, especially when driving a car. My beloved 1998 Acura RL recently exhibited a strange behavior at 239K miles, after making a turn the steering wheel would stay tilted in the direction of the last turn instead of straightening out. The auto mechanic pinpointed the failure to the ball joints, … Read More
To deploy a GPU-based SPICE solution, you need to understand the costs involved. To get your hands on this new report analyzing this specific issue, all you need to do is attend Empyrean’s upcoming webinar, “GPU-Powered SPICE: The Way Forward for Analog Simulation,” which will be held on Thursday, August 8, 2019, at 10:00 am (PDT).… Read More
My first professional experience with computers and file permissions was at Intel in the late 1970s, where we used big iron IBM mainframes located far away in another state, and each user could edit their own files along with browse shared files from co-workers in the same department. I saw this same file permission concept when … Read More
Verification engineers are the unsung heroes making sure that our smart phone chips, smart watches and even smart cars function logically, without bugs or unintended behavior. Hidden bugs are important to uncover, but what approach is best suited for this challenge?
With the Universal Verification Methodology (UVM) there’s… Read More
The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More
The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability… Read More
