Agentrys Designs a Real Chip with its Multi-Agent Workforce

The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as Frontier AI, the engineering tasks that use EDA can now be automated. These changes bring a new level of EDA impact within reach; continuously improving engineering workflows that determine quality, productivity, and time-to-market.

Agentrys is one of the new breed of EDA suppliers. The company consists of an applied research team building the future of chip design. Agentrys recently published a compelling white paper that describes the use of its technology to build a production-grade chip. The results are remarkable, and a link is coming so you can read the whole story. But first let’s examine how Agentrys designs a real chip with its multi-agent workforce.

Framing the Problem

We all know that AI applications are exploding. Examples include recommendation, vision, speech, and other generative models. And every new workload wants its own datapath, its own numeric format, and its own energy-per-inference sweet spot. This creates a demand curve for new chips that is vertical, but the supply of expert chip design teams is flat.

This is the problem Agentrys is solving. The white paper describes how to compose a new, autonomous workforce in minutes, and how it converges on a sign-off-clean chip within hours to days. The process to achieve this on a real chip is detailed. The chip is called AgentCore, and the image at the top of this post is a photo of it. It is a compact, 32-bit embedded-class processor built on an open, royalty-free instruction-set architecture.

A few more details are worth mentioning. There is a lot more in the white paper. The instruction set of this design covers base integer operations — arithmetic, logic, loads and stores, branches and jumps — extended with a hardware integer-multiply subset and a control-and-status-

register interface for performance monitoring. The design deliberately omits heavier facilities such as hardware divide, floating-point, and vector units to keep the design small and legible.

What is an Autonomous Workforce?

Combining an existing EDA flow with new AI technology can create an end-to-end, long-running, fully autonomous multi-agent workforce that takes a chip from specification to sign-off-clean

layout, sharpening its own decisions as it goes. The white paper describes four items that do the heavy lifting. Here is a shortened summary of each. There is more in the white paper.

Hierarchical multi-agent orchestration: A top-level orchestrator that delegates to sub-system leads, each of which owns a coherent set of specialist agents.

Governed iteration loops: Every optimization or debug loop runs against an explicit, enforced iteration budget with a full per-iteration history. This is what keeps long-horizon autonomy from spiraling into a token sink rather than converging.

Objective-function agnosticism: This project optimizes XLOPS per watt, but the figure of merit is just a parameter. Swap in latency, area, energy-per-inference, or a weighted multi-objective and the closure machinery is unchanged.

Provenance and a compounding knowledge base: Every claim is backed by an artifact that has a checksum in a machine-readable manifest, with a living design document and an append-only event log, so trust is built in rather than bolted on. Underpinning it is a continuously-curated design knowledge base — microarchitectural recipes, tool-specific quirks, PPA-closure heuristics, hard-won sign-off lessons. Every agent draws on this to decide better and faster, so eachcompleted design sharpens the next.

A term used above is XLOPS. This is a generalized unit of useful work. It includes floating-point FLOPS, integer TOPS, and SIMD throughput; each retired operation is weighted by a factor that tracks its relative transistor cost, anchored so that one FP32 fused-multiply-add equals 1.0 (an INT32 MAC is 0.5, a memory op is 0.1, and so on across nine op-classes). There is more detail on how this all works, including a formal description of the XLOPS formula in the white paper.

The Results

To achieve the results presented, a workflow was composed as five cooperating sub-systems under a top-level orchestrator. Each sub-system owns a coherent slice of the design problem and hands a validated artifact bundle to the next. The forward path is linear, while the self-learning feedback edges (re-implement, re-verify, re-close) connect them back into loops. The five cooperating sub-systems are:

Input and Setup: Ingest the specification and the XLOPS/W objective and stand up the flow.

Front-End: Turns the specification and objective into synthesizable RTL.

Design Verification: Prove the RTL is bit-exact against a golden ISA reference.

Back-End: Synthesis, placement, routing, and PPA closure.

Sign-Off and Summary: DRC and antenna sign-off, plus the provenance manifest and summary.

Each sub-system runs its own bounded, self-learning iteration loop, and a central iteration budget ledger is the canonical record of how many iterations each consumed. This is the governance that keeps long-horizon autonomy convergent rather than open-ended.

A complete overview of the results delivered by this technology is presented in the white paper. The results are quite compelling; you really need to see it for yourself. To whet your appetite, the figure below illustrates how the system autonomously learns and optimizes results over time.

And here is a summary of the results achieved for the AgentCore design:

To Learn More

If you are struggling to understand how to effectively add AI to your design flow, Agentrys can help. This white paper will show you the way, with real data to illustrate what can be achieved. You can get your copy of the white paper here.  You can also learn more about this exciting new company in an interview with its CEO on SemiWiki here. And that’s how Agentrys designs a real chip with its multi-agent workforce.

Also Read:

Agentrys a New Paradigm for Semiconductor Engineering at 2026 DAC

CEO Interview with Mark Ren of Agentrys