Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering

At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from RTL to tapeout. This is an example of loop engineering: designing the objectives, actions, evaluators, state, and failure-handling mechanisms that connect each result to the next design change.

Agentrys has applied this approach to XiangShan, a Linux-class RISC-V processor, with the goal of improving performance, power, and area for a specific workload. The workflow autonomously proposed and evaluated design changes using correctness checks, synthesis, place-and-route, and timing analysis. In eight hours, it found a configuration that improved throughput by 40% while reducing power by 28% and area by 10% relative to the reference design.

The figure at the top of this post summarizes these substantial results. Agentrys has published an “extend the frontier” case study that describes this work in some detail, which is transforming chip optimization. A link is coming but first let’s summarize the key items that are covered in this important piece as we learn how Agentrys shows the way with agentic loop engineering.

From AI Assistance to Autonomous Chip Design

Artificial intelligence is rapidly moving beyond assisting semiconductor engineers with individual tasks. A new approach, known as agentic loop engineering, promises to transform chip design by enabling AI systems to autonomously explore architectural alternatives, modify RTL implementations, evaluate results, and continuously improve designs with minimal human intervention.

In the new case study, Agentrys demonstrates how this approach can be extended into a coordinated, autonomous design optimization workflow. Using its Agentrys Studio Platform, the company applied agentic loop engineering to XiangShan.  In just eight hours, the workflow identified the substantial improvements discussed above when compared with an expert-tuned reference design.

These improvements demonstrate the potential of AI-driven optimization to explore design alternatives that conventional engineering approaches might overlook. What follows are some of the topics covered in the case study.

The Challenge: Navigating an Enormous Design Space

Modern processor design requires engineers to balance competing performance, power, and area (PPA) objectives. Increasing execution resources can improve instruction throughput but may increase power consumption, silicon area, and critical-path delays. Reducing resources can save energy but potentially compromise performance.

These trade-offs become especially difficult when thousands of architectural parameters interact. The XiangShan processor presented a demanding test case. Its design contained approximately 143,000 lines of Chisel code across 528 source files, with 3,284 adjustable parameters organized into 17 microarchitectural subsystems.

The primary benchmark was GAP BFS, a graph-processing workload characterized by irregular memory accesses. Approximately 88% of execution cycles were spent stalled on memory. This created an important optimization opportunity: processor structures contributing relatively little to workload performance could potentially be reduced or redesigned to save power and area.

Rather than manually exploring thousands of possible configurations, Agentrys used autonomous agents to identify and evaluate promising alternatives.

Two Interconnected Optimization Loops

The key architectural innovation is a system of two tightly coupled optimization loops.

The outer loop optimizes microarchitecture. It explores choices such as pipeline widths, cache configurations, queue depths, and register-file sizes. By reducing the dimensionality of the parameter space and using predictive models, the system concentrates expensive physical-design evaluations on candidates most likely to improve PPA.

The inner loop optimizes RTL implementation. It identifies inefficient hardware structures through switching-activity analysis and applies targeted transformations, including clock gating, operand isolation, dataflow bypass, register forwarding, retiming, and removal of unnecessary logic.

These loops operate cooperatively rather than independently. The case study details how this is achieved. The result is a continuously improving exploration process that learns from previous evaluations instead of restarting with each configuration.

Physical Results, Not Just AI Predictions

A major challenge with AI-driven design optimization is ensuring that proposed improvements translate into functioning silicon implementations. Agentrys addresses this through a shared evaluation workflow incorporating compilation, correctness checking, cycle-accurate simulation, synthesis, physical implementation, and timing and power analysis.

Candidates that fail required checks are rejected before advancing. This distinction matters because designs that appear attractive at the architectural level can fail to meet timing once implementation effects are considered.

The workflow uses predictive models to select promising candidates, but final optimization decisions are grounded in implementation measurements rather than predictions alone. With approximately 50 physical evaluations, the system explored enough of the design space to identify a significantly improved set of alternatives.

The Results: Better Performance with Lower Power and Area

The optimized XiangShan configuration achieved improvements across several critical metrics. These are summarized in the figure below.

Importantly, the optimized configuration satisfied a 1.5 GHz timing objective that the reference configuration could not meet. The system also identified multiple viable designs representing different trade-offs among performance, power, frequency, and area.

This collection, known as a Pareto frontier, enables engineers to select the configuration best aligned with their product requirements rather than accepting a single supposedly optimal result. For example, another configuration achieved approximately 0.84 W power consumption and 0.134 mm² area at 1.5 GHz, trading some throughput for lower energy requirements.

A New Model for Semiconductor Engineering

The implications extend beyond a single RISC-V processor. Agentrys Studio separates its orchestration framework from the underlying architecture, workloads, design tools, and implementation targets. This creates a framework that can incorporate proprietary RTL, commercial EDA tools, internal engineering scripts, and specialized AI agents.

The study used an open-source ASIC implementation environment, but the platform architecture is designed to support other toolchains and FPGA targets.

The broader opportunity is to shift engineering effort away from repetitive trial-and-error optimization and toward defining objectives, constraints, evaluation methodologies, and architectural priorities. Engineers establish what the design must accomplish. Autonomous agents explore how best to accomplish it.

The Future Is Continuous, Autonomous Optimization

Agentic loop engineering represents an important evolution in AI-enabled semiconductor development. Rather than using AI simply to generate RTL or recommend changes, this approach creates an integrated system capable of proposing, implementing, measuring, and refining designs through repeated feedback.

The XiangShan demonstration illustrates what becomes possible when architectural exploration, RTL optimization, verification, and physical analysis operate within a coordinated autonomous workflow.

While results will vary across workloads, technologies, and architectures, the central message is compelling: AI’s greatest contribution to chip design may come not from individual design recommendations, but from its ability to orchestrate and continuously improve the entire optimization process.

That could fundamentally change how future chips are designed—and how quickly engineers can discover better implementations.

To Learn More

I have just covered a high-level summary of this important work here. To get the whole story, download the new Agentrys case study here. And that’s how Agentrys shows the way with agentic loop engineering.