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Ultra-low Power IP for Wearables

Ultra-low Power IP for Wearables
by Paul McLellan on 07-28-2015 at 7:00 am

Wearables and the Internet of Things (IoT) in general are all about low power. Everyone must have read (or even experienced) the phenomenon of putting something like a Fitbit on and then after a short period leaving it in a drawer or putting it to recharge and forgetting about it for weeks. The longer devices can last the more likely they are to be successful. The biggest complaint about the Apple watch seems to be battery life, it barely lasts a day.

But wearables and IoT are not just about the actual device, they are also about communication infrastructure and computing/storage infrastructure. It is all about partitioning intelligence between the device and the cloud and ensuring that the data can be transmitted efficiently between them. Power is important in all of these areas. Even datacenters are power limited, although obviously at a completely different tradeoff point from wearables.

eSilicon has a lot of experience with low power design in all three of the IoT segments. They have an extensive portfolio of internally developed special purpose memories and register files and experience with special low-power processes:

  • ultra low power and ultra low voltage SRAM and ROM
  • pseudo-DP SRAM
  • low-leakage SRAM
  • 65nm, 55nm, 40nm, 28nm at TSMC, GlobalFoundries, SMIC and more

IoT mobile computing requires low-power high-performance embedded memories. IoT medical requires low-power and low-voltage embedded memories. And IoT computing requires low-power high-density embedded memories optimized for microcontrollers and processors. Although there is some overlap, these segments have largely different requirements.

eSilicon also provides STAR Navigator that allows design groups to explore the IP portfolio risk-free. They can download all the views of the IP (except the physical layout) so that they can easily do rapid prototyping, experiments, comparisons and generally “try before you buy”. This is all handled through an online portal and doesn’t require interacting with salesmen or placing a purchase order. Of course, if eventually you want to tape out a chip using some of the IP you “tried” you do have to eventually “buy” it to get access to the physical layout.

eSilicon also have another service called STAR Optimizer. This makes use of a lot of internal big-data analytics on all the designs eSilicon have seen and allows a design that is far enough along to be further optimized, sometimes with subtle changes like changing the core voltage of a memory but not the periphery, or swapping out one bit cell for a different one, or varying the process spread and trading off a little yield for lower power. This provides a very structured way to get access to the captured design expertise of a team that has done a lot more designs than any one design group is likely to have done.

For example, here is an interface ASIC in 28nm with 17M gates and about 42Mb memory subsystem. The goal was the lowest possible standby power and idle power. By making changes, standby power was reduced by 8X and idle power by 20X.

 Another important recent development for low power is that TSMC has gone back and produced new ULP (ultra low power) versions of some of its mature processes such as 40nm. Other foundries have also been returning to older nodes, not just pushing on to FinFET, since designs are now spread across the process spectrum depending on what features they require. By remapping designs from 40LP to 40ULP there is considerable reduction in leakage power which has a major impact on SRAM leakage in particular (and many chips are dominated in area/leakage by SRAM).

IoT designs are likely to go through a sequence where initially they are built out of standard products until it is clearer what optimized solutions can be created using silicon level design and IP. But a lot of differentiation is going to come from the ability to choose and deploy low power semiconductor IP.

The eSilicon STAR portal is here.