IP the eSilicon Way

Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn’t know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.

At Electronic Design Process Symposium (EDPS) held last week Patrick Soheill who is VP of the IP BU gave the eSilicon perspective on IP. He started with his version of the “Moore’s Law is Over” graph showing costs going up at 20nm. Funnily enough the week before I was at GSA Silicon Summit and a lot of people on the panel said the graphs are wrong and costs are going down. Then when that finished I went to U2U, the Mentor users group meeting and heard that the Samsung keynote had pretty much said costs are not going down, and then I went to a TSMC session and they said that 16nm would not be a cost-reduction node. We’ll just have to wait and see.

Anyway, the eSilicon worldview is that they are going up (or if down then not much). But people are not going to really be prepared to pay more for the same transistors so the things that is going to fill the gap is IP. In advanced technologies, memory is dominating the chip so having really good memory IP is very important. Guess what that group in Vietnam primarily does. Redundancy is a fact of life in memory design. With billions of bits then 3 sigma doesn’t get you there but there are no tools for 5-6 or even 7 sigma.

Good memory design is a balancing act between redundancy, test logic, process stuff (redundant vias, planarity friendly, wire spreading), and on-chip variation (OCV) guardbanding. If you don’t spend the money then the yield goes down. If you spend too much you don’t get a return.

The processes are now so complex that the IP and the process have to be cooptimized in the early stages. Low level metal capacitance and resistance is an issue. Gate capacitance in FinFETs. Variation in general. It is no longer possible for a foundry to put together a process and then tell everyone to take-it-or-leave-it. There has to be early test-chips, risk manufacturing and so on.

The other approach is the More Than Moore using 3D. The yield can potentially be much higher and it can stretch out the life of 28nm for a long time. If the graphs about 20nm are true then 28nm is not just cheaper than ever process that came before, it is cheaper than all processes after it too. In some sense it is the sweet spot. The current 2.5D interposer approach can work although there are two big problems: cost and the so called known-good-die problem (if a bad die gets onto the interposer it takes down several good die with it).

Patrick’s conclusions:

• costly and intricate manufacturing as we move past 28nm
• challenging lithography and new EDA tools to handle it
• the ecosystem needs to work together: design, EDA, IP, foundries
• new emerging solutions to extend existing IP have new challenges

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