VLSI Symposium 2020 – Imec Buried Power Rail

The 2020 VLSI Technology Symposium was held as a virtual conference from June 14^th through June 19^th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.

As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch of 21nm for N4 then 16nm at N3, 16nm is challenging. The height of a standard cell in logic is the metal pitch multiplied by the number of metal tracks, a recent trend in device scaling is to reduce the track height. The current state-of-the-art is a 6-track cell. One thing limiting track height is the power rails that are typically double width due to resistance issues. If you bury the power rials in the substrate you can reduce the track height to 5 tracks and relax the metal pitch requirement back to 21nm for N3.

Figure 1. Conventional scaling cliff.

BPR also enable novel architectures such as CFETs and back-side power distribution.

Figure 2. BPR technology.

The challenges with BPR are that you need a low resistance and reliable metal line that does not contaminate the Front End Of Line (FEOL). BPR is inserted early in the process flow and must stand up to all the heat of the device formation steps.

Figure 3. BPR process.

A lot of work on BPR has been done with Ruthenium (Ru) because it has low resistance for narrow lines and is very stable, but Ru is very expensive. This work looks at Tungsten (W) as an alternative. I ran some numbers on Ru versus W for cost and for the same film thickness I estimate Ru is approximately 40x the cost of W. There is a lot more experience with W and the cleans are well known so contamination shouldn’t be an issue. Ru has better line resistance for very narrow lines but W meets the target of 50ohms/µm with a CD around 32nm and an aspect ratio of around 6.

The process to integrate the W BPR starting once the trench is etched is:

1. Deposit a 7nm silicon nitride (SiN) barrier to prevent metals migrating out of the trench.
2. Deposit 4nm titanium nitride (TiN) liner.
3. Deposit the W with 5nm of Atomic Layer deposition (ALD) and then fill with Chemical Vapor Deposition (CVD) plus silicon dioxide (SiO) CVD to form an oxidation barrier.
4. Chemical Mechanical Planarization (CMP) of the SiO.
5. Dry etch recess the SiO and W-TiN sidewalls to prevent shorting.
6. Deposit a 7nm SiN plug barrier.
7. SiN fill using a Floable CVD (FCVD) process + anneal and CMP.

Figure 4. Full integration.

Figure 4 shows BPR integrated with W metal 0 but Imec has also shown good results when M0 is Ru with a Ru via connecting to the buried W.

The electrical results from the process show no degradation in the device performance and good electromigration. BPR can provide a 20% scaling boost and the addition of a backside power distribution can provide another 30%. In summary the Imec work presents a promising alternative material for BPR with lower cost.

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