Intel Node Names

There is a lot of interest right now in how Intel compares to the leading foundries and what the future may hold.

Several years ago, I published several extremely popular articles converting processes from various companies to “Equivalent Nodes” (EN). Nodes were at one time based on actual physical features of processes but had become uncoupled from physical features and a “marketing number”.

My original articles were based on some work ASML did and that they allowed me to extend and publish. Basically, what they did was plot node versus Contacted Poly Pitch (CPP) multiplied by Minimum Metal Pitch (MMP) for all the leading logic producers and come up with a curve fit that could be used to assign node numbers to the processes using a consistent methodology. The problem with the original method of calculating EN is that scaling began to transition to include Track Height (TH) and Single versus Double Diffusion Break. I eventually adopted transistor density in millions of transistors per millimeter squared using a weighted average of 60% two input NAND cells and 40% Scanned Flip Flop cells based on an Intel metric. The resulting number more completely captured logic scaling but is different than nodes that people are used to.

If you look at the leading edge logic landscape today, there are two foundries, Samsung and TSMC and one IDM, Intel still pursuing the state of the art in logic. The foundries are following a “foundry” node roadmap of 65nm, 40nm, 28nm, 20nm, 16nm/14nm, 10nm, 7nm, 5nm, 3nm. Intel on the other hand has stayed with a more classic node sequence of 65nm, 45nm, 32nm, 22nm, 14nm, 10, 7nm, 5nm. Furthermore, because the scaling node to node is generally larger for Intel than the foundries, the node names no longer align.

While considering this situation the other day it occurred to me, I could resurrect EN by plotting node versus transistor density. I decided my approach would be to use TSMC as the baseline since they are the clear logic density leader, I took TSMC’s nodes from 28nm to a projected 1.5nm and plotted the nodes versus transistor density and fitted a curve, see figure 1.

Figure 1. TSMC Nodes Versus Transistor Density.

 The curve fit in figure 1. has an excellent R squared value of 0.9879. Using the equation for the curve fit I can take Intel nodes and generate node numbers based on TSMC’s node scaling (EN).

TSMC has announced timing and density improvements through the 3nm node. Assuming TSMC stays on a two-year cadence for new nodes and continues to produce shrinks per generation like the 5nm and 3nm nodes, we can project transistor density versus node out to 1.5nm.

Intel has provided guidance on 7nm timing and density improvements and we then assume Intel gets back on a two year cadence with 2x shrinks (the same as 7nm) and project transistor density for Intel. I should note here that Intel took 3 years to get 14nm into production, 5 years to get 10nm into production and is now heading towards 3 to 4 years for 7nm. I would therefore view this as an aggressive roadmap for Intel.

Figure 2 provides our roadmap for node by year for TSMC and node and EN by year for Intel.

Figure 2. TSMC and Intel Node Roadmaps.

We are projecting that Intel’s 7nm node will have an EN value of 4.1nm (intermediate between TSMC 5nm and 3nm nodes), the Intel 5nm node will have an EN value of 2.4nm (intermediate between TSMC 3nm and 2nm nodes) and if Intel stays with a 2x per generation shrink the Intel 3nm node could have an EN vale of 1.3nm or slightly better than TSMC’s 1.5nm. This of course presupposes intel can execute 2x shrinks at a much faster pace than in the past.

This roadmap for Intel while aggressive still leaves them playing catch up versus TSMC until at least mid-decade.

This roadmap is purely density based and Intel products generally require higher performance than most of TSMC’s customers. As best as we can benchmark Intel versus TSMC processes for performance, we believe Intel 10SF is competitive with TSMC 7nm. I would expect Intel 7nm to be competitive with TSMC 3nm and Intel 5nm to be competitive with TSMC 2nm.

If Intel is reading this I would suggest they could do everyone a favor and rename 7nm to 4nm and 5nm to 2.5nm so they are named more consistently with how the processes actually compare to the other logic leaders.

In conclusion this analysis provides a way to convert Intel nodes into equivalent TSMC nodes and provides roadmaps for both companies into the late 2020s. Even with aggressive execution Intel will likely be competitive with TSMC at best and likely trailing them until mid-decade even under the best case scenario.

Also Read:

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

IEDM 2020 – Imec Plenary talk

No Intel and Samsung are not passing TSMC