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Smart TV Chipset: 4 Key Takeaways from Interconnect IP

Smart TV Chipset: 4 Key Takeaways from Interconnect IP
by Majeed Ahmad on 01-26-2016 at 4:00 pm

The ultra high-definition (UHD) or 4K TV hardware is leading to insanely powerful chipsets in the age of Netflix, and that is taking the system-on-chip (SoC) design to a whole new level of complexity. Take the case of Samsung’s new chipset for SUHD TVs that boasts more than 100 IP interfaces.

Here, apart from the usual suspects like CPU, GPU, memory subsystems and peripherals, the new IP offerings include image processing, overlay and picture-in-picture (PIP) functions. Samsung’s new chipset—powering select models of its high-end LCD TVs with 4K resolution—requires greater bandwidth efficiency because it has to process more information per pixel.

Samsung has licensed Arteris FlexNoC IP for use in select smart TV models

Not surprisingly, therefore, the image and vision processing capabilities equipped with computationally intensive algorithms are going to play a critical role in these SUHD TV models. The image and vision processing features also go hand in hand with application processing tasks that are tied up to the open-source Tizen operating system.

Samsung’s new SUHD TV models—unveiled at the 2016 CES—are powered by the Tizen OS, which supports web standards for TV app development and can download and install apps on Samsung’s smart TVs just like mobile phones. It’s worth noting that Samsung uses the “SUHD” marketing term for its 4K LCD TVs.

Interconnect IP: Key Takeaways

Coming back to Samsung chipset and more than 100 IP that it supports, the Korean semiconductor giant is using the Arteris FlexNoC interconnect fabric to ensure optimal connections that serve as the backbone in this large and powerful chipset. The FlexNoC on-chip interconnect will help Samsung reduce die size and cost as well as meet the conflicting bandwidth and latency requirements.

Here are the key takeaways that SoC powerhouse Samsung seems to have drawn from using the Arteris’ FlexNoC interconnect backbone.

1. Debugging Features

The Arteris FlexNoC technology offers on-chip debug visibility, trace and statistics collection. The observability—which comes with the debugging features of FlexNoC interconnect IP—is software programmable and it encompasses probes, trace and performance counters.

Furthermore, the on-chip debug visibility is integrated with debug infrastructure and tool chains, including ARM and Lauterbach. Next up, timeout and watchdog features in FlexNoC help in the challenging situations, for instance, when an individual IP block hangs.

2. Multiprotocol Support

The multiprotocol support in FlexNoC interconnect IP facilitates the use of multiple standards defined by different entities such as ARM AMBA and OCP. That plays a vital role in creating a large and complex chip like the one used in Samsung SUHD TV while reducing power consumption and die area.

Arteris has recently expanded its support for the ARM Microcontroller Bus Architecture (AMBA) protocols to confront the rising amount of complexity in SoC designs. Arteris aims to provide support for the current and future versions of AMBA standards such as AXI, AXI Coherency Extensions (ACE) and Coherency Hub Interface (CHI).

FlexNoC IP eases communication bottlenecks among subsystems in large SoCs

3. Quality-of-Service (QoS)

Samsung’s SUHD TVs are striving to become the Internet of Things (IoT) control hub while allowing consumers to discover and access a vast amount of content ranging from movies to games to TV programs. Here, bandwidth boost and latency control are crucial in order to ensure superior picture quality in Samsung’s smart TVs with the 4K display.

The FlexNoC interconnect fabric from Arteris ensures on-chip data flow with concurrent bandwidth and latency mechanisms. That allows large chipsets to transmit master/initiator QoS information throughout the interconnect all the way to the target.

4. 4K Resolution

If bandwidth defines smart TV’s ability to deliver TV apps, the shift from 1080p to 4K hardware sets the tone for higher resolutions a.k.a. more pixels. The hardware for ultra high-definition or 4K resolution brings more color pixels and higher frame rates, but at the same time, the imaging and vision subsystems add more strains to the overall SoC fabric.

A chipset with a robust interconnect backbone can efficiently adapt to the algorithms for color enhancement and resolution boost. Arteris’ FlexNoC on-chip IP backbone preps 4K chips to better handle these complex algorithms without raising the power consumption and size of the chipset.

Also read:

Interconnect Watch: 3 Chip Design Merits for Network Applications

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design

Is Interconnect Ready for Post-mobile SoCs?

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