The RISC-V and Open-Source Functional Verification ChallengeMost of the RISC-V action at the end…Read More
Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers2.5D package design is rapidly finding its stride…Read More
Addressing Reliability and Safety of Power Modules for Electric VehiclesAs electric vehicles (EVs) gain widespread adoption, safety,…Read More
Shaping Tomorrow’s Semiconductor Technology IEDM 2024Anyone who has read my articles about IEDM…Read More
SI and PI Update from Cadence on Sigrity XSignal Integrity (SI) and Power Integrity (PI) issues…Read More
"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO
Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address … Read More
During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!
According to Morris Chang:
“For… Read More
Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital… Read More
Process Design Kit (PDK) development is one of the most entertaining things to watch in the semiconductor design world. It is kind of like the Golden Snitch in the game of Quidditch. No matter how rough EDA vendors play the game, no matter what the score is, it’s the vendor that “gets” the Golden PDK Snitch that wins the semiconductor… Read More
“IP Innovation is moving from component level to system level”. This mantra was heard during the conference, from various speakers: during the keynote talk by Ganesh R. from Gartner and presentation “Integration-Optimized IP from Cadence” by Ranga Srinivasan, also during discussion around coffee (or a glass … Read More
The Common Platform Technology Forum last week was not well attended, less than half than the GlobalFoundries Conference. It was deja vu of previous CP forums but there were a couple of surprises to go with the disappointment. The lunch line was long, but fortunately I was escorted to the press lunch featuring VIP’s from Samsung,… Read More
I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.
In the old days each foundry would have to staff up… Read More
The most impressive devices at CES this year by far were the Android tablets, I absolutely want one. It will not replace my laptop but my laptop will no longer leave the house (my laptop AC adapter weighs more than a tablet!) My iPod will be for walks and the gym, I won’t buy another digital camera, and no e-reader for me.
SemiWiki is a cloud… Read More
Seriously, I would vote for Aart, he would make a great California Governor. You will probably not meet a more fiscally responsible CEO. Synopsys is one of the best run companies in Silicon Valley and was recently rated in the top 25 on social media site glassdoor.com. Aart ( SNPS ) has a 92% approval rate, Wally ( MENT ) 80%, Lip-Bu ( … Read More
Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.
Sudhakar Jilla,… Read More
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