ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.
Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies. Using a full-chip modeling approach, it can verify that a design meets ESD guidelines and identify vulnerable areas of the design. It can report if current density exceeds limits for wires and vias. It works for both digital and analog circuits.
There are three different types of analysis.
Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.
Pathfinder is used in two different ways. Early in the design it can be used for ESD planning, especially on bumped chips which need to contain extensive ESD protection circuitry in the core and not just in an IO ring. If this is not done, and ESD protection circuitry is only added very late in the design process, it risks causing unexpected area (and perhaps timing) problems and thus potentially major schedule impact. The second way is to analyze the final design to signoff on the ESD protection prior to tapeout.Share this post via:
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