Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.
What’s New from Cadence in Virtuoso 6.1.5
- Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform db files, generate layout from schematic source improved )
- Connectivity Design (smarter wire to via automation, better auto routing for bus and diff pair, one router simplifies setup time, low power using Common Power Format with visual spreadsheet)
- Design Constraints (in schematic add layout constraints for Encounter, constraint checking simplified, constraints are bi-direction schematic-layout)
- Selective Automation (reliability analysis integrated, fluid guard rings without tweaking Pcell code )
- Parasitic Aware Design (how does physical layout affect performance, schematic-> constraints-> tests and sims -> pre-layout parasitic estimates -> circuit optimization -> MODGEN creation -> device placement -> net routing -> in-design verification -> extraction -> parasitic comparison)
- Use 6.1 like you did 5.1, there’s no benefit
- Take advantage of new features to get benefits
Karim Khalfan talked about the SOS tool used by IC designers:
- Hardware Configuration Management – should be easy to use
- Design Management is for the entire IC team
- Manage everything: Spec, RTL, Verification, P&R, Analog, Custom Layout
- Large teams, multiple sites, data explosion, binary files, complex flows, IP and re-use, design variants
- Version control – text and binary files, folders, tags and labels
- Release management – take snapshots
- Issue tracking – connect to your favorite tools
- Design reuse – reference previous projects
- Global Collaboration – client/server architecture, cache, synched
- Authentication – users identified, groups (schematics, layout, etc.)
- Design Aware Integration – integrated into Virtuoso
- Hardware Design
- Easy to checkin and checkout, use design objects
- Disk use is optimized, not sending terabytes across network
- Isolated and shared work spaces, you decide
- Design hierarchy can be managed
- Visual differences – compare schematics or layouts, click on each change
- Integration directly into Virtuoso
- DDM is built just for IC designs, no 3rd party SW needed
Then Karim did a live demo of Virtuoso 6.1.5 with ClioSoft menus (Design Manager) and commands explained as he went through the process of checking in cells and checking out cells for an IC project. Used both the Library Manager and Schematic tools in Virtuoso. Visual Difference shown between two versions of a schematic or layout, flat or hierarchical.
Cadence and ClioSoft have really created a powerful and flexible IC design environment for team-based design. Both the designers of schematics and the layout people will benefit from using hardware configuration management by keeping track of their complex projects all within the familiar Virtuoso tools.
How Avnera uses Hardware Configuration Management with Virtuoso IC Tools
Hardware Configuration Management and why it’s different than Software Configuration Management
Webinar: Beyond the Basics of IP-based Digital Design ManagementShare this post via:
There are no comments yet.
You must register or log in to view/post comments.