Here in the Silicon Forest (Oregon) we have a venture-backed, fabless analog semi company called Avnera that has designed over 10 Analog System on Chips (ASoC). Their chips are used in consumer products for both wireless audio and video applications.
James Rollins is the director of physical design at Avnera and I learned how they design these ASoC with Virtuoso and Hardware Configuration Management (HCM).
Questions and Answers
Q: What kind of IC experience does your design team have?
A: On average our team has over 18 years experience in areas like RF, analog, digital, DSP and embedded systems.
Q: Where do you design the chips?
A: Both here in Beaverton, Oregon and in California.
Q: What IC design tools do you have?
A: We use Cadence Virtuoso for our design environment.
Q: When you design blocks in your chips how many iterations would they typically go through?
A: Up to 50 iterations to get the desired low power, high audio quality and best wireless connectivity.
Q: What were you looking for in a HCM tool?
A: Basically an HCM system that felt invisible to users, helped us automate our tool flow, enforced design conventions, and gave us notification of changes and a way to see changes.
Q: What was the install and setup like with SOS?
A: Within the first day we had SOS up and running the way we wanted it.
Q: How does SOS benefit your IC design process?
A: It protects our designers from accidentally loosing valuable data, plus it gets rid of manual tracking of design version details.
Q: Describe how your verification engineers use the HCM tool.
A: The DV engineers can configure different versions of the design as they perform verification. They can update test benches whenever parts of the design have been changed because they receive notification. For every test they know that the blocks are up to date.
Q: Does an HCM help you experiment a bit?
A: Our designers feel a little more free to play around to achieve the best results. You can experiment with subtle changes when you have a tool like SOS at your disposal. If a problem pops up, we can always roll back the changes.
Q: How did you get started with your HCM setup?
A: We had a meeting with ClioSoft to discuss our two design locations then decided to setup the SOS design data repository, a central filer in Oregon. In California we used a cache server that is automatically synchronized by SOS.
Q: Using that setup what is the benefit?
A: This has a major positive impact on network bandwidth requirements since a change in one block doesn’t not require copying the entire design or library during synchronization. A designer can go to any Avnera center and have access to their latest work.
Q: What does each designer see on their computer?
A: SOS gives each designer a private work area for their own development that can synch with all of the other work that is happening at the same time. A change made in Oregon can be seen by other designers in both Oregon and California.
Q: Would I use an HCM even with only one design center?
A: Yes, I’d use SOS even with a single design center. If you do have a remote office, then it’s mandatory.
Q: How does check-in work?
A: When the designer is happy with their work, they check-in that version so that it becomes available to the entire team. The design, documentation and the test bench for that block are all being managed by the SOS tool.
Q: When does a designer’s work area get updated?
A: The SOS tool can automatically handle that synch, but for our work we allow each designer control over when the synch happens.
Q: What kind of tool flow automation did you use?
A: With the ClioSoft tool we used the “Exec Before” and “Exec After” features during check in to run a set of automated tasks: netlisting of schematics, signal name compliance, and a “diff file” to show layout engineers what changed.
Q: Tell me more about visual differences.
A: We started using the Visual Design Diff (VDD) feature to automatically highlight the changes between two versions of a schematic or a layout. Inside of a Virtuoso editor window we can see the changes highlighted.
Q: When you integrate all of these analog and digital blocks into the final chip, what are the challenges?
A: It’s a challenge to debug the effects of top-level parasitics during chip integration. Small changes to a block’s behavior can make a large difference on the top-level routing and the parasitic values.
Q: How does the SOS tool help you with timing closure?
A: We do floor planning and routing, then run DRC and extraction to get a new netlist with parasitics. If timing or other measurements don’t meet spec then we can quickly switch out versions of blocks and then resimulate in order to pinpoint where the root cause is located.
Q: What other tips do you have for HCM users?
A: Use notes and tags to track your changes.
Q: Are you using compute farms in your design flow?
A: Yes, in Oregon we have compute farms and that lets our California designers remotely launch large jobs because the data is up to date and available.
Avnera is using Cadence Virtuoso IC tools with ClioSoft SOS as their HCM to successfully design ASoC chips for the highly competitive consumer wireless audio and video markets.
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