Power has become the strongest driver of semiconductor design today, more important than area, more important than timing. Whether the device is handheld, like a wireless phone, or tethered, like a router, complex power and energy requirements must be met. Shrinking geometries continue to impose new challenges as power management techniques and methodologies evolve to keep up.
Power consumption used to be verified at the gate-level, often too late to make any significant changes without major impact on the chip schedule. This is no longer good enough. The battery life of a handheld device can impact its competitiveness and the cooling and packaging choices for networking devices can make the profitability plummet. Power needs to be addressed and understood early in the design flow to have a meaningful impact.
Power management is not limited to lowering power alone. The design of the power delivery network (PDN) is a critical aspect of ensuring power integrity of the SoC. Excessive voltage sagging, for example, can cause timing failures or even result in the wrong value being latched. However, the impracticality of running gate level simulations means it is too late by the time vectors are available to identify some of these failure conditions (see figure which shows how a large change in current drawn by the chip coupled with package inductance can cause a large swing in voltage, and in turn in a timing failure ).
Instead, register transfer level (RTL) power analysis can be used to address power early in the design flow. At that level there is good visibility of where, when and why activity and power is going. It is the highest level of hardware abstraction where it has the capacity and performance to do full-chip power analysis while maintaining good accuracy. Moreover, RTL power can drive floorplanning and PDN design early in the design flow, versus traditional guesstimates and spreadsheets. During PDN power integrity sign-off, utilizing RTL simulations to uncover worst-case switching scenarios can also lower risks of potential chip failures.
Apache’s Power Model Methodology has three components, to manage power early in the design flow:
- ·PowerArtist, which enables RTL power analysis and reduction. With simulation vector analysis, what-if exploration of different power architectures, automatic RTL power reduction, and a powerful environment for visual and textual power debug, it addresses power at RTL in all respects. In particular, RTL power metrics and analyses can drive key decisions on power grid and package.
- ·RedHawk, which allows early PDN prototyping without compromising accuracy. With huge capacity, RedHawk is designed tohandle entire chips maintaining signoff accuracy and accurately calculates the effects of simultaneous switching nose (in core, memory and I/O), decoupling capacitance (intentional and intrinsic) and on-chip and package inductance. In particular, the power grid prototyping enables the on-die power grid required to meet the design’s power constraints coming in from PowerArtist.
- ·The Chip Power Model (CPM) is Apache’s compact but Spice-accurate model of the full-chip power delivery network. Redhawk can create this to enable package selection and design with Sentinel, Apache’s chip-package-system (CPS) co-design, co-analysis solution.
During early stages of the design flow, when the major architectural and packaging decisions are still not finalized, the Apache methodology enables
- ·Early PDN prototyping to facilitate optimum power grid sizing, supply pad and decap requirements, IO pad placement and floorplanning
- ·RTL-power driven creation of a full-chip spice-accurate PDN model that can then drive early package design and selection
During sign-off, the Apache methodology enables:
- ·Confidence signing off power integrity and package, via higher coverage across power-critical switching scenarios identified from RTL simulations
- ·Superior realistic vectorless for power integrity analysis, guided by quantified RTL power data
In summary, full RTL to Silicon Power Integrity.
Apache’s Power Model Methodology white-paper
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