Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am

Metal1 Via Metal2 s

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The  connections to all the devices needs to have the most… Read More


Automotive Upate at Arm DevSummit from VW

Automotive Upate at Arm DevSummit from VW
by Daniel Payne on 10-20-2020 at 10:00 am

audi etron

Although our family has down-sized to just one vehicle, my dream car is still a Tesla, both because it’s an EV and they have a vision for autonomous vehicles. At the recent Arm DevSummit I watched a fireside chat with Alexander Hitzinger, CEO of Artemis, the skunkworks at Audi, part of the Volkswagen Group.  I knew that Audi … Read More


CEO Interview: Jason Xing of Empyrean Software

CEO Interview: Jason Xing of Empyrean Software
by Daniel Payne on 04-24-2020 at 10:00 am

empyrean

It’s been about seven years since Randy Smith last interviewed Jason Xing, the President/CEO of North America for Empyrean Software, so the timing felt good for a fresh update. I’ve been watching Empyrean at DAC for several years now, and have come away impressed with their growth and focus on some difficult IC design… Read More


Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that

Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
by Daniel Payne on 08-24-2018 at 12:00 pm

There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More


A New Kind of Analog EDA Company

A New Kind of Analog EDA Company
by Daniel Payne on 07-10-2018 at 12:00 pm

My IC design career started out with circuit design of DRAMS, so I got to quickly learn all about transistor-level design at the number one IDM in the world, Intel at the time. In the early days, circa 1978 we circuit designers actually had few EDA tools, mostly a SPICE circuit simulator followed by manual extraction, manual netlisting,… Read More


What to Expect from Methodics at DAC

What to Expect from Methodics at DAC
by Daniel Payne on 06-21-2018 at 12:00 pm

I’ve been visiting DAC for decades now, at first as an EDA vendor and since 2004 as a freelance EDA consultant. There’s always a buzz about what’s new, semiconductor industry trends, who is getting acquired and the latest commercial EDA and IP offerings. There’s so much vying for my attention at DAC each… Read More


Worldwide Design IP Revenue Grew 12.4% in 2017

Worldwide Design IP Revenue Grew 12.4% in 2017
by Daniel Nenni on 05-11-2018 at 7:00 am

When starting SemiWiki we focused on three market segments: EDA, IP, and the Foundries. Founding SemiWiki bloggers Daniel Payne and Paul McLellan were popular EDA bloggers with their own sites and I blogged about the foundries so we were able to combine our blogs and hit the ground running. For IP I recruited Dr. Eric Esteve who had… Read More


Automotive Mega-trends, Safety and Requirements Management

Automotive Mega-trends, Safety and Requirements Management
by Daniel Payne on 01-30-2018 at 12:00 pm

I come from a car-centric family where my father actually bought and sold over 300 vehicles in his lifetime, so automotive mega-trends pique my interest. A new conference called Semiconductors ISO 26262 held it’s first annual event last month, meeting in Munich with guest speakers from some impressive companies like: … Read More