Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping SystemQualifying an AI-class RISC-V SoC demands proving that…Read More
DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Note that there are several DAC deadlines coming up in the next couple of weeks.
The deadline for user track submissions is January 17th (next Tuesday). Submission requires an extended abstract. See here for details.
The deadline for DAC workshops is January 19th (next Thursday). A proposal is required. See here for details.
The… Read More
Just because it seems that the likes given to: Interface Protocols, USB3, HDMI, MIPI… the winner and losers in 2011 were numerous, I decided to count it.
Twenty-four likes received, in 11 Linkedin groups (see below), that’s good! Very goos! Thanks to all of you… And most probably thanks to IPNESTfor the quality of the… Read More
There is one semiconductor company that for the last 3 years has outperformed ARM and more than doubled in stock price relative to Apple. They are everywhere but barely known to most. The success of this company in the coming year though could result in the leveling of AMD and nVidia as they try to adjust to the economics of the mobile… Read More
One of the fun things when a company gets big but is still private, like Atrenta, is that you start to get invited to events like the Needham Growth Conference that took place earlier this week in New York. When I ran Compass Design Automation, which at the time was about $55M in revenue, I remember going to a couple of these events. At … Read More
EDAC (EDA consortium) market statistics service announced the data for Q3 of 2011. Revenue increased 18.1% (versus 2010) to $1543.9 million. Sequentially (versus Q2) revenue increase 7.4%. Annualized, that puts EDA at over $6B for, I belive, the first time ever. Wally Rhines, who is EDAC chair (and CEO of Mentor) commented that… Read More
Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.
To meet these new requirements for performance and power, memory… Read More
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More
As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More
One of the most significant announcements at the consumer electronics show (CES) this week was Intel’s Medfield, an Atom-based smartphone SoC. The SoC itself is unremarkable, perhaps a little better than ARM Cortex-based SoCs in some areas, worse in others. The reason it is significant is that Motorola (soon to be Google,… Read More
Virtual fabric sounds like something that would be good for making the emperor’s new clothes. I talked today to Les Spruiell of Imera to find out what it really is.
Anyone who has worked as either a designer or as an EDA engineer has had the problem of a customer who has a problem but can’t send you the design since it is (a)… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot