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IC Power Dissipation in…the New York Times!

IC Power Dissipation in…the New York Times!
by Paul McLellan on 08-05-2011 at 4:37 pm

Generally if you want to read about power dissipation in SoCs and the potential impact on limiting how much computer power we might be able to cram onto a given piece of silicon then EE Times is a good place to look. But last weekend there was a full-length article in, of all places a different Times, the New York Times, entitled ProgressRead More


Apple Strength Will Compel ARM to Trim its Sails

Apple Strength Will Compel ARM to Trim its Sails
by Ed McKernan on 08-03-2011 at 7:00 pm

ARM’s move into the broad Tablet and PC space is based on lining up as many partners as possible to attack Intel from multiple angles. It’s a strategy not so different from what Intel employed in the early PC days. However, the strategy is unraveling as Apple and Samsung have reached market share domination without ARM’s merchant… Read More


Apple makes 2/3 of profits of entire mobile industry

Apple makes 2/3 of profits of entire mobile industry
by Paul McLellan on 08-02-2011 at 5:41 pm

This is an amazing picture (click to enlarge). Apple now makes 2/3 of all the profit in the entire mobile handset industry. And that is the entire handset industry, not just smartphones where it has also blown past Nokia to become number one (although there are more Android handsets than iOS, those handsets are spread across multiple… Read More


Has IP moved to Subsystem? Will IP-SoC 2011 bring answers?

Has IP moved to Subsystem? Will IP-SoC 2011 bring answers?
by Eric Esteve on 08-02-2011 at 11:21 am

I have shared with you the most interesting I have heard during IP-SoC 2010, in two blogs, Part I was about IP market forecast(apparently my optimistic view was quite different from the rather pessimistic vision shared by SC analysts) and Part II, named “System Level Mantra”, was strongly influenced by Cadence clever presentation,… Read More


PathFinder webinar: Full-chip ESD Integrity and Macro-level Dynamic ESD

PathFinder webinar: Full-chip ESD Integrity and Macro-level Dynamic ESD
by Paul McLellan on 08-01-2011 at 10:00 am

The PathFinder webinar will be at 11am Pacific time on Thursday 4th August. It will be conducted by Karthik Srinivasan, Senior Applications Engineer at Apache Design Solutions. Mr. Srinivasan has over four years of experience in the EDA industry, focusing on die, system, and cross-domain analysis. His professional interests… Read More


MCU Performance Customers: The Cavalry is Coming Over The Hill

MCU Performance Customers: The Cavalry is Coming Over The Hill
by Ed McKernan on 07-31-2011 at 7:30 pm

cavalry lg

The under the radar, sleepy microcontroller market is about to undergo a rapid transformation the next several years with new entrants and the rise of 32 bit cores that will redefine the parameters for success. This will revive growth and result in new winners and losers. But lots of questions remain.

My first job out of college in… Read More


Smart Fill Replaces Dummy Fill Approach in a DFM Flow

Smart Fill Replaces Dummy Fill Approach in a DFM Flow
by Daniel Payne on 07-30-2011 at 7:11 pm

I met with Jeff Wilson, Product Marketing Manager at Mentor in the Calibre product group to learn more about Smart Fill versus Dummy Fill for DFM flows. Jeff works in the Wilsonville, Oregon office and we first meet at Silicon Compilers back in the 1990’s.

Dummy Fill

This diagram shows an IC layout layer on the left as originallyRead More


Totem webinar: Analog/Mixed-Signal Power Noise and Reliability

Totem webinar: Analog/Mixed-Signal Power Noise and Reliability
by Paul McLellan on 07-30-2011 at 5:26 pm

The Totem webinar will be at 11am on Tuesday 2nd August. This session will be conducted by Karan Sahni, Senior Applications Engineer at Apache Design Solutions. Karan has been with Apache since 2008, supporting the Redhawk, Totem, Sentinel product lines. He received his MS in Electrical Engineering from the Syracuse University… Read More


CDNS EDA360 is DEAD!

CDNS EDA360 is DEAD!
by Daniel Nenni on 07-30-2011 at 3:00 am

Hard to believe EDA360, the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat!, is DEAD at the ripe old age of one. As you may have already read John Bruggeman left Cadence after the company conference call last week. The formal announcement should go out on Monday after the SEC… Read More


Cache Coherency and Verification Seminar

Cache Coherency and Verification Seminar
by Paul McLellan on 07-27-2011 at 5:45 pm

At DAC Jasper presented a seminar with ARM on cache coherency and verification of cache coherency. The seminar is now available online for those of you that missed DAC or missed the seminar itself.

Cache architectures, especially for multi-core architectures, are getting more and more complex. Techniques originally pioneered… Read More