The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)The Impact of AI on Software and Hardware…Read More
Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
GaN HEMT modeling with ANN parameters targets extensibilityDesigners choosing gallium nitride (GaN) transistors may face…Read More
It is interesting watching as changes in technology bring giants to their knees. Far and away the best book on the subject is Clayton Christensen’s The Innovator’s Dilemma. If you haven’t read it then rush out and buy it immediately. In tech, you are not educated if you haven’t.
Two things made me think … Read More
FineSim is Magma’s circuit simulator that has been doing extraordinarily well. In my opinion it is one of the big reasons that Synopsys is acquiring (presumably, still subject to approval of course) Magma. FineSim is especially strong in the memory market with over 70% of the top 5 DRAM manufacturers and the top 10 flash manufacturers… Read More
Things you don’t know about Virtuoso: we’ve got you cornered.
That is the title on a Cadence blog item last week. It is actually about variability and how to create various corners for simulation and analysis, but given Cadence’s franchise for Virtuoso, its lock-in through SKILL-based PDKs and so forth, it … Read More
Even if ExpertIO acquisition by Synopsys, coming after nSys acquisition a couple of months ago, will not have a major impact on Synopsys’ balance sheet, it will again change the Verification IP market landscape. The acquisition of Inventure, a subsidiary of Zuken, will have a major impact on the Interface IP market, even if it’s… Read More
One thing I do as an internationally recognized semiconductor blogger is listen to the quarterly conference calls of companies that drive our industry. TSMC is always interesting, I really like the honesty and vision of Dr. Morris Chang. Cadence is good, I always want to hear what Lip-Bu Tan has to say. Oracle and Larry Ellison, … Read More
At DVCon on Thursday March 1st (St David’s day for any Welsh readers) Jasper is sponsoring lunch from 12pm to 1.30pm. It will take place in the Cascade/Sierra ballrooms.
During lunch there will be a panel discussion Formal Verification from Users’ Perspectives with real users no how they mitigate risk in their designs… Read More
On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”
My response was, “Yes, however only the parts that we have been able to simulate.”
Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More
Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More
At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm,… Read More
It has been a great conundrum to many of the 20[SUP]th[/SUP] century trained economists and Harvard’s Kennedy School of Government folks as to why a government led massive spending spree and Ben Bernanke’s non-stop printing presses can’t at least engender a mediocre economic recovery.
I blame 21st century Moore’s Law!
Today’s… Read More
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