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Using OTP Memories for High-performance Video

Using OTP Memories for High-performance Video
by Paul McLellan on 11-01-2013 at 4:15 pm

 One of the most demanding applications where semiconductors are used is in the various applications of digital video from tablet computers, to home entertainment. iPad with a retina display is already at high-definition (HD) resolution (2048×1536) and all indications are that video is racing towards what is known as 4K resolution, also known as ultra high definition, 3840×2160 pixels which is roughly four times the pixels and so four times as demanding as HD.

One of the leaders in digital TV processing (and other home control and connectivity applications) is Sigma Designs. Coincidentally they were also our lead beta customer when I was CEO at Envis. Doing high performance video is hard enough, but doing it within a tight power budget is a real challenge. Our power-reduction tool Chill wasn’t compelling enough for them to adopt it but they just announced their selection of OTP (one-time-programmable) memory supplier and it is Sidense.

Sigma have signed a multi-year license to use Sidense SHF OTP macros. These are used in advanced processes from 40nm down to 16nm FinFET. Sigma will start by using SHF in a 40nm implementation, which has already been qualified in G and low-power/low-leakage variants, for set-top-box (STB) and digital TV applications. In some sense this is a continuation of an existing relationship: Sigma have been a customer of Sidense since 2008 and have products in production using older technologies.

The factors that make Sidense attractive for these applications are:

  • small area (so low cost)
  • no mask or process changes to standard digital process (so low cost)
  • high security: there is no visible difference between a 0 and 1 bit cell, even etching the die down, and no charge is held on the bitcell
  • advanced node coverage (20nm now, 16nm in qualification)
  • high performance at low power (both active and standby)


An SHF module consists of an OTP core (the bitcell array), charge pump hard macro for in-field programming (generates the non-standard voltages required), device access port (DAP) providing access through 16/32 bit parallel bus and SBPI, which provides serial and byte-wide interfaces with SPI-compatible protocols. Read speeds are as low as 20ns depending on configuration and process and (at 28/20nm) a 1us/bit write speed.


At the recent TSMC OIP meeting, Sidense revealed the advanced process roadmap for design, characterization and qualification (above). FinFET structure aligns well with Sidense OTP implementation (which is antifuse and basically depends on forming a tiny crystal in the gate-oxide, technically known as dielectric breakdown induced epitaxy). For all nodes down to 40nm, IP9000 qualification is complete. It is in progress for 28nm and 20nm. 16nm is at the test chip stage.

There is more information about Sidense SHF memories here.


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