The Invisible Bottleneck Is Costing You Time You Can't Get BackBy Joel Jorgensen, FlowAccel. The 2026 Siemens EDA…Read More
Arm targets the agentic AI era with new edge, cloud and robotics platformsArm is expanding its computing platform for an…Read More
Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AIInstead of tweaking existing designs, VSORA built an…Read More
UWB Without the Integration Headache: Ceva and LG Bring Precision to More ChipsCeva and LG Electronics have joined forces to…Read More
That’s too bad, as you have missed latest news about the Hybrid Memory Cube (presentation by Micron), Wide I/O 2 standard, as well as other standards like LPDDR4, eMMC 5.0, and LRDIMM,the good news is that you may find all these presentations on MemCon proceedings web site.
I first had a look at Richard Goering excellent blog: wideI/O… Read More
Layout editing is a complex task, traditionally done manually by designers, and the layout design productivity largely depends on the designer’s skills and expertise. However, a good tool with features for ease of design is a must. Layout productivity has been an area of focus and various features are constantly being added in… Read More
OK. I was wrong. Microsoft did buy Nokia’s handset business. For $7.2B, which for a company that just wrote off nearly $1B on tablets isn’t that much. Nokia is a company that had a peak valuation of $110B although it is not clear how much of that is in the deal versus out of the deal.
Details from Reuters here.
Elop is expected… Read More
You can only design and optimize for low-power SoC designs if you can actually simulate the entire Chip, Package and System together. The engineers at ANSYS-Apachehave figured out how to do that and talked about their design for power methodology in a webinar today. I listened to Arvind Shanmugavel present a few dozen slides and… Read More
IP is the center of the semiconductor universe and nobody knows this better than Design and Reuse. The D&R website was launched in 1997 targeting the emerging commercial semiconductor IP market. Today, with more than 15,000 IP/SOC product descriptions updated daily, D&R is the #1 IP site matching customer requirements… Read More
One of the challenges in doing a complex analog or mixed signal design is that things get out of step. One designer is tweaking the schematic and re-simulating, another is tweaking the layout of transistors, another is changing the routing. This is not because the design flow is messed up, but rather it reflects reality. If you wait… Read More
The history of TSMC and its Open Innovation Platform (OIP) is, like almost everything in semiconductors, driven by the economics of semiconductor manufacturing. Of course ICs started 50 years ago at Fairchild (very close to where Google is headquartered today, these things go in circles). The planarization approach, whereby… Read More
Here, I am talking about reliability of chip design in the context of electrical effects, not external factors like cosmic rays. So, the electrical factors that could affect reliability of chips could be excessive power dissipation, noise, EM (Electromigration), ESD (Electrostatic Discharge), substrate noise coupling and… Read More
Real Heroes have many different jobs. My oldest son is a Math Teacher, he is a hero. You may have read about him before, he is the co-developer and administrator of SemiWiki. Think about it, without math where would the world be today?
My other son is a Fireman, Emergency Medical Technician, and also a hero. He is at the Rim Fire in Northern… Read More
All chips have critical power management requirements, often with multiple supply voltages. Digital power management ICs (PMICs) are commonplace to convert unregulated voltages from batteries and noisy power supplies to fully regulated accurate power to keep even the most sensitive chips performing.
Powervation is a company… Read More
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ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance