Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AI

Instead of tweaking existing designs, VSORA built an AI chip from scratch to fix the real bottleneck: moving data fast enough to keep the math circuits busy.

There’s a version of the AI hardware story that everyone in the chip industry has heard a hundred times. A startup raises money on a clever chip design, promises to topple Nvidia, the gorilla that dominates AI hardware, and then, somewhere between finishing the design and getting the first real chips back from the factory, learns a hard lesson. The difficult part was never building the circuits that do the math. The difficult part was everything around them: the software everyone already uses, and the constant struggle to move data fast enough to keep those math circuits busy.

Historical DNA of VSORA

VSORA came at the problem from the opposite end. That reversal is the most interesting thing about the company.

Its founders spent about a decade at a company called DiBcom, where they became the world leader in mobile-TV chips, the silicon that lets phones, handhelds, automotive, and consumer PC devices receive live television. Then two large German automakers handed them a brutal assignment: build a single chip that could be configured for the various global standards where they were selling their cars. At the time each standard had its own specific chipset and DiBcom replaced those with a single solution.

No off-the-shelf chip could do it. The usual tool for this kind of job is a digital signal processor (DSP), a chip built to handle streams of audio, video, or radio data, but none on the market was flexible enough nor had enough compute power. So the team built their own. It was a processor with a repertoire of ~100 operation/instruction types executable in a single tick of its clock, paired with custom software to program it. Making a chip that flexible and run that fast meant solving enormous coordination problems: keeping every operation in step, managing the flow of work through the chip, and routing data to the right place at the right moment.

It was, by the team’s own admission, a “nightmare,” but it worked. DiBcom designed multiple chips both digital and RF, prior to the final solution, and all together led to 14 tape-outs. That experience inspired the company to define a couple of principles to drive any future development: design for the long haul, and build on open, widely shared software foundations.

In 2015, the core team of DiBcom regrouped and incorporated VSORA to design an advanced DSP solution that could utilize LLVM as the backbone compiler. In 2017 the IP was released and discussions with the automotive people started around this timeframe. In 2018/2019, their automotive partners pushed them toward machine learning.

VSORA’s DSP Already Covered Roughly 90% of All AI Inference

What the team didn’t expect was how neatly that DSP core would map onto artificial intelligence. They took stock of what an AI chip would require, and found they had already built roughly 90 percent of it: dense grids of multiply-and-add circuits (the single operation that essentially all AI math boils down to), the ability to move large amounts of data at once, and the internal plumbing to keep both fed. See figure 1.

The direction of that overlap is the crucial point. The heart of an AI chip is a grid of circuits that all do the same simple thing: multiply two numbers, add the result to a running total, and do so over and over, in lockstep. It’s enormously powerful, but it’s repetitive and predictable. The TV chip DiBcom had already built was the harder machine: flexible, reconfigurable, doing many different things at once and keeping them all coordinated. Having solved the harder problem first, the team realized an efficient AI chip wasn’t a leap into something new. It was a natural next step from hardware they already understood deeply.

The strategy that followed is worth understanding. Building and using an AI model involves two very different phases. Training is the one-time, extremely expensive process of teaching a model, and it’s the phase where Nvidia’s software, specifically, a toolset called CUDA that nearly all AI programs are written for, gives it a nearly unbreakable hold on customers. Inference is what happens every time you actually use a trained model to answer a question, generate text, or make a decision. Inference runs constantly 24/7, at massive scale, and that’s where the real day-to-day cost of running AI is decided.

Just as important for deployment, the VSORA software stack can run an existing model on a VSORA processor, by exporting the model from a familiar framework such as PyTorch to ONNX, and passing it through VSORA’s proprietary compiler, built on the open source LLVM compiler, which optimizes the model and generates hardware-specific code for VSORA’s tensor-processing and DSP cores, thus eliminating the need to hand-write the low-level GPU kernels that CUDA requires.

VSORA skipped the training fight it couldn’t win and went straight for inference. And it aimed at the single biggest bottleneck in that world, one engineers call the “memory wall.” The problem is this: a modern AI chip can do math far faster than it can be fed the data it needs to work on. So the expensive math circuits spend most of their time sitting idle, waiting for the model’s data to arrive from memory. VSORA’s priority wasn’t the big headline speed number on a spec sheet. It was the number that actually matters: how much of that rated speed the chip delivers on real work.

VSORA’s Jotunn8: From Design to Silicon

That approach is now backed by a real, working chip called Jotunn8. It’s built on an advanced 5-nanometer manufacturing process, with the processor and its memory co-packaged in a single 2.5D chiplet module. It has a rated peak of 3.2 petaFLOPS in FP8 precision, that’s 3.2 quadrillion math operations per second, and 288 gigabytes of fast memory. The design was sent to the factory in October 2025, in partnership with the manufacturing specialists GUC and TSMC (the world’s leading chipmaker), and the first physical chips came back in May 2026. Currently, performance characterization is underway.

The payoff shows up in efficiency. VSORA claims Jotunn8 keeps its math circuits usefully busy more than 50 percent of the time on real workloads. Conventional GPUs, by comparison, often deliver 10 percent or less of their rated peak on the same memory-bound work, burning power and money while their circuits wait. And VSORA reports doing it on less than half the power versus leading GPUs running inference.

That result puts VSORA among a small group of companies capable of the highest tier of data-center AI inference, and makes it the only European player at that level, according to VSORA.

A funding round in July 2026, led by the investment firm Ardian alongside Otium, the European Innovation Council Fund, and other new and existing backers, is now paying for the push to get the chip into customers’ hands.

Conclusion

Whether the design wins in practice will be settled where these things always are: in the racks of real data centers, over the coming year. But the logic holds together. A veteran team took a deep expertise in complex, flexible chip design, sidestepped a software war it had no path to winning, and bet the company on the plain economics that will decide whether AI can keep growing without its costs spiraling out of control.

Lauro Rizzatti is a business development executive at VSORA, a semiconductor company building high-performance silicon for AI inference. He is a noted consultant and industry expert on chip design verification and hardware emulation.

Also Read:

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VSORA Board Chair Sandra Rivera on Solutions for AI Inference and LLM Processing

Inference Acceleration from the Ground Up