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Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.
As the saying goes, it’s… Read More
Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.… Read More
The ever-growing demand for longer battery life in mobile devices and energy savings in general have pushed power optimization to the top of designers’ concerns. While various techniques like multi-VT transistors and clock gating offer power savings at gate-level design, the real impact occurs at system level, where hardware… Read More
Traditional simulation-based power analysis methods face insurmountable challenges to accurately capture complex designs activities in real-world scenarios. As the scale… Read More
When we last saw Luc Burgun’s name in the semiconductor industry, he was CEO and co-founder of EVE (Emulation and Verification Engineering), creator of the ZeBu (Zero Bugs) hardware emulator. EVE was acquired by Synopsys in 2012.
After the acquisition, Luc moved out of EDA and became an investor. Join me as I catch up with Luc and … Read More
Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.
While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today,… Read More
Bill Neifert invited me to join him on Zoom recently to talk about his move to Corellium, a company known within the DevSecOps (development, security, operations) market. Developers and security groups use its virtualization technology to build, test, and secure mobile and IoT apps, firmware, and hardware.
Not knowing much … Read More
The Design Automation Conference, as always, is a good barometer on the state of EDA and my area of interest, verification. The recent DAC offered plenty of opportunities to check on trends and the status quo.
Remarkably, exhibitors and attendees were upbeat about the chip design landscape despite concerns about supply chain … Read More
I learned about Kandou a year ago and liked what I heard, as should anyone who wants higher res displays and faster downloads from their electronic devices. I’ve been tracking Kandou since and believe it’s living up to its goal to be the undisputed innovator in high-speed, energy-efficient chip-to-chip link solutions to improve… Read More
In another departure from my chip design verification “beat,” I took a look at Kandou and like what I learned.
Kandou from Lausanne, Switzerland, boasts “Kandou It” as its tagline and as it should be if Kandou’s USB-C multi-protocol retimer solution with USB4 support is inside next-gen laptops, notebooks, desktops, tablets and… Read More
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Has ASML Reached the Great Wall of China