Author: Lauro Rizzatti

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VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone Survives

VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone Survives
by Lauro Rizzatti on 10-13-2026 at 8:00 am
Categories: Semiconductor, VSORA

Sandra Rivera and the inference era

Sandra Rivera, Chair of VSORA, joined Bloomberg’s The Close in July for an interview on the current state of AI. What follows is a summary of that conversation.

When a Silicon Valley veteran who once ran Intel’s Data Center and AI Group, and now chairs a French inference-chip challenger, sits down with a tech journalist from Bloomberg,… Read More

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Built to Deliver the Answer, Not to Train the Model

Built to Deliver the Answer, Not to Train the Model
by Lauro Rizzatti on 10-06-2026 at 8:00 am
Categories: Semiconductor, VSORA

VSORA SemiWiki Post Sep 28 2026 Week


How VSORA rebalances memory and compute for AI inference in the data center and at the edge

For more than a decade, the AI hardware industry focused mainly on model training, while inference represented a smaller share of overall demand. That balance is changing as trained models are deployed widely in recommendation engines, … Read More

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Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing

Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing
by Lauro Rizzatti on 09-29-2026 at 12:00 pm
Categories: Lithography

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Recently, I had the opportunity to speak with Johann Foucher, founder and CEO of Pollen Metrology, a French company whose journey offers a rare vantage point on how artificial intelligence is reshaping semiconductor manufacturing from the inside out. What makes Pollen Metrology’s story compelling isn’t just … Read More

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Silicon Valley, à la Française – One Year On

Silicon Valley, à la Française – One Year On
by Lauro Rizzatti on 09-23-2026 at 8:00 am
Categories: Semiconductor, VSORA

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One Year Later — September 2026

When this piece first ran a year ago, VSORA was the quiet outsider, a company with a bold architecture and no Silicon Valley address. One year on, the thesis has held up better than even its author expected. In January 2026, Sandra Rivera, former CEO of Altera and, before that, a two-decade Intel veteran… Read More

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Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AI

Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AI
by Lauro Rizzatti on 09-16-2026 at 6:00 am
Categories: Semiconductor, VSORA

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Instead of tweaking existing designs, VSORA built an AI chip from scratch to fix the real bottleneck: moving data fast enough to keep the math circuits busy.

There’s a version of the AI hardware story that everyone in the chip industry has heard a hundred times. A startup raises money on a clever chip design, promises to topple… Read More

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Unified Emulation and Prototyping: Pipedream or Reality?

Unified Emulation and Prototyping: Pipedream or Reality?
by Lauro Rizzatti on 09-03-2026 at 10:00 am
Categories: EDA, Emulation, FPGA, Synopsys

Unified Emulation and Prototyping Pipedream or Reality Figure 1

Preamble
Hardware-assisted verification (HAV) platforms, including hardware emulators and FPGA-based prototyping systems, are the two dominant methodologies for validating long workloads on complex System-on-Chip (SoC) designs before tape-out. HAV sits within a broader continuum of verification engines: simulation… Read More

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From Detection to Safety: Reframing Fault Simulation for Functional Safety

From Detection to Safety: Reframing Fault Simulation for Functional Safety
by Lauro Rizzatti on 07-06-2026 at 10:00 am
Categories: EDA, Synopsys

From Detection to Safety Figure 1

In the early 1980s, when computer-aided engineering (CAE), the precursor to modern electronic design automation (EDA), was just taking shape, my professional trajectory shifted in a way that would prove foundational. I joined Teradyne, the Boston-based leader in automated test equipment (ATE), and I encountered for the first… Read More

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When Software Outruns Silicon: Hardware-Assisted Test Generation to the Rescue

When Software Outruns Silicon: Hardware-Assisted Test Generation to the Rescue
by Lauro Rizzatti on 06-29-2026 at 2:00 pm
Categories: EDA, Synopsys

When Software Outruns Silicon Figure 1

For the past decade, the semiconductor industry has been moving in one direction: shift-left, specifically, shifting more validation into the pre-silicon phase. The idea was straightforward: if software ultimately determines how a system behaves, then software should become a primary vehicle for verification.

The industry… Read More

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The Great Divide: A Tale of Three Hardware Emulation Architectures

The Great Divide: A Tale of Three Hardware Emulation Architectures
by Lauro Rizzatti on 05-06-2026 at 10:00 am
Categories: EDA, Emulation, Synopsys

A Tale of Three Hardware Emulation Architectures

Hardware emulation arose as a necessity out of the needs of the eighties. By the mid-1980s, semiconductor designs had outgrown the practical limits of gate-level simulation. Gate-level simulation delivered accuracy, but at glacial pace; silicon prototypes performed at real-speed but arrived far too late. The industry needed… Read More

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From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding

From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding
by Lauro Rizzatti on 04-13-2026 at 6:00 am
Categories: EDA, Synopsys

From Wooden Boards to White Gloves Table 1 (1)

FPGA prototyping and hardware emulation originated from two independent demands that emerged at roughly the same time, namely, the necessity to implement digital designs in reconfigurable hardware. This was conceivable given the newly introduced field programmable gate array (FPGA) device.

Yet from the very beginning they… Read More