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OTP Memory to Build Smarter Power Management

OTP Memory to Build Smarter Power Management
by Paul McLellan on 08-29-2013 at 11:20 pm

 All chips have critical power management requirements, often with multiple supply voltages. Digital power management ICs (PMICs) are commonplace to convert unregulated voltages from batteries and noisy power supplies to fully regulated accurate power to keep even the most sensitive chips performing.

Powervation is a company that uses a multiprocessor SoC architecture for its digital power management solutions. The architecture comprises a proprietary dual core (DSP and RISC) processor, both RAM and Sidense one-time-programmable (OTP) memory, power conversion blocks, serial interfaces and more.

Powervation’s digital power management SoC products use two types of memory to perform the functions needed for their features and to provide for users. Firmware and DSP code, along with security codes and design and user-specific configuration parameters for the voltage regulator, are stored in Sidense 1T-OTP.

When the device is powered on, the contents of the OTP memory are loaded to a RAM for fast access to the processing unit. 1T-OTP provides long-term storage of vital code that determines power supply functionality, so it is crucial that this memory be reliable.

 Sidense’s antifuse-based split-channel bit-cell architecture (1T-Fuse) in 1T-OTP minimizes bit-cell area (and its impact on total chip area) while allowing the memory to be fabricated in standard CMOS processes with no additional masks or process steps, and thus no extra processing cost. The single transistor architecture leads to very small size and the memories generate all the voltages needed both for programming and reading the memory, so no unusual power supplies are required. The antifuse technology is irreversible so that once programmed a bit cannot be “forgotten.”

Using Sidense OTM memories like this is much more cost effective than either putting other non-volatile memory technologies such as flash onto the chip, or alternatively using a separate off-chip memory or ROM. One chip is almost always a lot cheaper than two. For parameters that change occasionally, the Sidense technology can be used to create a pseudo few-time-programmable memory that Sidense calls emulated multi-time programmable (eMPT) operation. The registers are replicated a number of times and can be reprogrammed that many times, with the latest programming being picked up when the rmemory is read. For parameter memories that are typically small, this has negligible overhead especially when compared to other more expensive technologies such as flash.

The Sidense/Powervation white paper is here.

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